Optimize H573RI/H503KB/H503RB clock config. #2507
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Complement of stm32duino#2506 Signed-off-by: Kazuki Ota <[email protected]> Co-Authored-by: Frederic Pillon <[email protected]>
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Basically same as "Optimize PLL ratio" in #2506.
Summary
This PR fixes/implements the following bugs/features
By setting
SRC / M = 2N = 250for PLL1/2/3 you can flexibly determine clock source frequency and easily calculate division P/Q/R.CubeMX Screenshots
for H503KB/H503RB
for H573RI
