Merge pull request #99 from siliconcompiler/rice/adds_asyncfifo_almost_full

Adds async fifo almost full signal + cocotb test

Author: RiceShelley

.github/workflows/ci.yml

@@ -26,8 +26,8 @@ jobs:
           pip install .[dev]
           flake8 --statistics .
 
-  check_paths:
-    name: Run CI
+  python_ci:
+    name: Run Python Only
     runs-on: ubuntu-latest
     steps:
       - name: Check out Git repository
@@ -44,7 +44,7 @@ jobs:
           mkdir testrun
           cd testrun
 
-          pytest $GITHUB_WORKSPACE
+          pytest $GITHUB_WORKSPACE -m "not eda"
 
   lint_verilog:
     name: Lint Verilog Code
@@ -75,3 +75,24 @@ jobs:
         if: success() || steps.check-format.conclusion == 'failure'
         run: |
           verible-verilog-lint --rules_config ./.github/workflows/config/verible.rules `cat files.txt`
+
+  eda_ci:
+    name: Run EDA
+    runs-on: ubuntu-latest
+    container: ghcr.io/siliconcompiler/sc_runner:latest
+    steps:
+      - name: Check out Git repository
+        uses: actions/checkout@v4
+      - name: Run tests
+        run: |
+          python3 -m venv .venv
+          . .venv/bin/activate
+
+          pip install --upgrade pip
+          pip install .[dev]
+
+          # change running directory
+          mkdir testrun
+          cd testrun
+
+          pytest $GITHUB_WORKSPACE -m "eda"

lambdalib/ramlib/rtl/la_asyncfifo.v

@@ -21,36 +21,39 @@
  ****************************************************************************/
 
 module la_asyncfifo #(
-    parameter DW    = 32,        // Memory width
-    parameter DEPTH = 4,         // FIFO depth
-    parameter NS    = 1,         // Number of power supplies
-    parameter CTRLW = 1,         // width of asic ctrl interface
-    parameter TESTW = 1,         // width of asic teset interface
-    parameter CHAOS = 0,         // generates random full logic when set
-    parameter PROP  = "DEFAULT"  // Pass through variable for hard macro
+    parameter DW                = 32,       // Memory width
+    parameter DEPTH             = 4,        // FIFO depth
+    parameter ALMOSTFULL        = 0,        // FIFO depth
+    parameter NS                = 1,        // Number of power supplies
+    parameter CTRLW             = 1,        // width of asic ctrl interface
+    parameter TESTW             = 1,        // width of asic teset interface
+    parameter CHAOS             = 0,        // generates random full logic when set
+    parameter PROP              = "DEFAULT" // Pass through variable for hard macro
 ) (  // write port
     input                  wr_clk,
     input                  wr_nreset,
-    input      [   DW-1:0] wr_din,        // data to write
-    input                  wr_en,         // write fifo
-    input                  wr_chaosmode,  // randomly assert fifo full when set
-    output reg             wr_full,       // fifo full
+    input      [   DW-1:0] wr_din,         // data to write
+    input                  wr_en,          // write fifo
+    input                  wr_chaosmode,   // randomly assert fifo full when set
+    output reg             wr_full,        // fifo full
+    output reg             wr_almost_full, // fifo almost full
     // read port
     input                  rd_clk,
     input                  rd_nreset,
-    output     [   DW-1:0] rd_dout,       // output data (next cycle)
-    input                  rd_en,         // read fifo
-    output reg             rd_empty,      // fifo is empty
+    output     [   DW-1:0] rd_dout,        // output data (next cycle)
+    input                  rd_en,          // read fifo
+    output reg             rd_empty,       // fifo is empty
     // Power signals
-    input                  vss,           // ground signal
-    input      [   NS-1:0] vdd,           // supplies
+    input                  vss,            // ground signal
+    input      [   NS-1:0] vdd,            // supplies
     // Generic interfaces
-    input      [CTRLW-1:0] ctrl,          // pass through ASIC control interface
-    input      [TESTW-1:0] test           // pass through ASIC test interface
+    input      [CTRLW-1:0] ctrl,           // pass through ASIC control interface
+    input      [TESTW-1:0] test            // pass through ASIC test interface
 );
 
     // local params
     localparam AW = (DEPTH == 1) ? 1 : $clog2(DEPTH);
+    localparam AFULLFINAL = (ALMOSTFULL != 0) ? ALMOSTFULL : DEPTH - 1;
 
     // local wires
     reg  [AW:0] wr_grayptr;
@@ -82,7 +85,7 @@ module la_asyncfifo #(
             wr_binptr[AW:0]     <= 'b0;
             wr_grayptr[AW:0]    <= 'b0;
         end else begin
-            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
+            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH[AW:0]) ? 'b0 : wr_binptr_mem_nxt[AW:0];
             wr_binptr[AW:0] <= wr_binptr_nxt[AW:0];
             wr_grayptr[AW:0] <= wr_grayptr_nxt[AW:0];
         end
@@ -114,7 +117,13 @@ module la_asyncfifo #(
         if (~wr_nreset) wr_full <= 1'b0;
         else
             wr_full <= (wr_chaosfull & wr_chaosmode) |
-                  (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH;
+                  (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH[AW:0];
+
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) wr_almost_full <= 1'b0;
+        else
+            wr_almost_full <=
+                  (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) > (AFULLFINAL[AW:0]-1);
 
     // Write --> Read clock synchronizer
     for (i = 0; i < (AW + 1); i = i + 1) begin
@@ -136,7 +145,7 @@ module la_asyncfifo #(
             rd_binptr[AW:0]     <= 'b0;
             rd_grayptr[AW:0]    <= 'b0;
         end else begin
-            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
+            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH[AW:0]) ? 'b0 : rd_binptr_mem_nxt[AW:0];
             rd_binptr[AW:0] <= rd_binptr_nxt[AW:0];
             rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
         end

lambdalib/ramlib/tests/__init__.py

@@ -0,0 +1,155 @@
+import cocotb
+from cocotb.triggers import RisingEdge
+from cocotb_bus.bus import Bus
+from cocotb.queue import Queue
+from cocotb.binary import BinaryValue
+
+
+class LaAsyncFifoWrBus(Bus):
+    """Cocotb bus for lambdalib async FIFO WR interface"""
+
+    _signals = ["wr_din", "wr_en", "wr_full"]
+    _optional_signals = ["wr_almost_full", "wr_chaosmode"]
+
+    def __init__(self, entity=None, prefix=None, **kwargs):
+        super().__init__(
+            entity,
+            prefix,
+            self._signals,
+            optional_signals=self._optional_signals,
+            **kwargs
+        )
+
+    @classmethod
+    def from_entity(cls, entity, **kwargs):
+        return cls(entity, **kwargs)
+
+    @classmethod
+    def from_prefix(cls, entity, prefix, **kwargs):
+        return cls(entity, prefix, **kwargs)
+
+
+class LaAsyncFifoRdBus(Bus):
+    """Cocotb bus for lambdalib async FIFO RD interface"""
+
+    _signals = ["rd_dout", "rd_en", "rd_empty"]
+    _optional_signals = []
+
+    def __init__(self, entity=None, prefix=None, **kwargs):
+        super().__init__(
+            entity,
+            prefix,
+            self._signals,
+            optional_signals=self._optional_signals,
+            **kwargs
+        )
+
+    @classmethod
+    def from_entity(cls, entity, **kwargs):
+        return cls(entity, **kwargs)
+
+    @classmethod
+    def from_prefix(cls, entity, prefix, **kwargs):
+        return cls(entity, prefix, **kwargs)
+
+
+class LaAsyncFifoSource:
+    """Driver for write side of lambdalib async fifo"""
+
+    def __init__(self, bus: LaAsyncFifoWrBus, clock, reset=None):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
+
+        self.queue = Queue()
+        self.width = len(self.bus.wr_din)
+
+        self._run_cr = cocotb.start_soon(self._run())
+
+        self.bus.wr_chaosmode.value = 0
+        self.bus.wr_en.value = 0
+
+        self.wr_en_generator = None
+
+    def set_wr_en_generator(self, generator):
+        self.wr_en_generator = generator
+
+    async def send(self, data):
+        await self.queue.put(data)
+
+    async def wait_until_idle(self):
+        while not self.queue.empty() or self.bus.wr_en.value == 1:
+            await RisingEdge(self.clock)
+
+    async def _run(self):
+        clock_edge_event = RisingEdge(self.clock)
+
+        bus_val = None
+
+        while True:
+            await clock_edge_event
+
+            fifo_full = self.bus.wr_full.value
+            wr_en = self.bus.wr_en.value
+
+            if bus_val is None:
+                bus_val = await self.queue.get()
+            elif wr_en and not fifo_full:
+                bus_val = None if self.queue.empty() else self.queue.get_nowait()
+
+            if bus_val is None:
+                self.bus.wr_en.value = 0
+            else:
+                self.bus.wr_en.value = next(self.wr_en_generator) if self.wr_en_generator else 1
+
+            self.bus.wr_din.value = bus_val if bus_val else 0
+
+
+class LaAsyncFifoSink:
+    """Driver for read side of lambdalib async fifo"""
+
+    def __init__(self, bus: LaAsyncFifoRdBus, clock, reset=None):
+        self.bus = bus
+        self.clock = clock
+        self.reset = reset
+
+        self.queue = Queue()
+        self.width = len(self.bus.rd_dout)
+
+        self._run_cr = cocotb.start_soon(self._run())
+
+        self.bus.rd_en.value = 0
+
+        self.rd_en_generator = None
+        self._pause = False
+
+    def set_rd_en_generator(self, generator):
+        self.rd_en_generator = generator
+
+    def pause(self):
+        self.bus.rd_en.value = 0
+        self._pause = True
+
+    def resume(self):
+        self._pause = False
+
+    async def read(self) -> BinaryValue:
+        return await self.queue.get()
+
+    async def _run(self):
+        clock_edge_event = RisingEdge(self.clock)
+
+        while True:
+            await clock_edge_event
+
+            fifo_empty = self.bus.rd_empty.value
+
+            if self._pause:
+                self.bus.rd_en.value = 0
+            elif self.rd_en_generator:
+                self.bus.rd_en.value = next(self.rd_en_generator)
+            else:
+                self.bus.rd_en.value = 1
+
+            if self.bus.rd_en.value and not fifo_empty:
+                self.queue.put_nowait(self.bus.rd_dout.value)