changed parameter name

Author: RiceShelley

lambdalib/ramlib/rtl/la_asyncfifo.v

@@ -23,7 +23,7 @@
 module la_asyncfifo #(
     parameter DW                = 32,       // Memory width
     parameter DEPTH             = 4,        // FIFO depth
-    parameter ALMOST_FULL_LEVEL = DEPTH-1,  // FIFO depth
+    parameter ALMOSTFULL        = 0,        // FIFO depth
     parameter NS                = 1,        // Number of power supplies
     parameter CTRLW             = 1,        // width of asic ctrl interface
     parameter TESTW             = 1,        // width of asic teset interface
@@ -53,6 +53,7 @@ module la_asyncfifo #(
 
     // local params
     localparam AW = (DEPTH == 1) ? 1 : $clog2(DEPTH);
+    localparam AFULLFINAL = (ALMOSTFULL != 0) ? ALMOSTFULL : DEPTH - 1;
 
     // local wires
     reg  [AW:0] wr_grayptr;
@@ -84,7 +85,7 @@ module la_asyncfifo #(
             wr_binptr[AW:0]     <= 'b0;
             wr_grayptr[AW:0]    <= 'b0;
         end else begin
-            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
+            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH[AW:0]) ? 'b0 : wr_binptr_mem_nxt[AW:0];
             wr_binptr[AW:0] <= wr_binptr_nxt[AW:0];
             wr_grayptr[AW:0] <= wr_grayptr_nxt[AW:0];
         end
@@ -116,13 +117,13 @@ module la_asyncfifo #(
         if (~wr_nreset) wr_full <= 1'b0;
         else
             wr_full <= (wr_chaosfull & wr_chaosmode) |
-                  (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH;
+                  (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH[AW:0];
 
     always @(posedge wr_clk or negedge wr_nreset)
         if (~wr_nreset) wr_almost_full <= 1'b0;
         else
             wr_almost_full <=
-                  (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) > (ALMOST_FULL_LEVEL-1);
+                  (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) > (AFULLFINAL[AW:0]-1);
 
     // Write --> Read clock synchronizer
     for (i = 0; i < (AW + 1); i = i + 1) begin
@@ -144,7 +145,7 @@ module la_asyncfifo #(
             rd_binptr[AW:0]     <= 'b0;
             rd_grayptr[AW:0]    <= 'b0;
         end else begin
-            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
+            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH[AW:0]) ? 'b0 : rd_binptr_mem_nxt[AW:0];
             rd_binptr[AW:0] <= rd_binptr_nxt[AW:0];
             rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
         end

lambdalib/ramlib/tests/tb_la_asyncfifo.py

@@ -60,7 +60,7 @@ async def test_almost_full(dut):
     await Timer(wr_clk_period_ns * random.random(), "ns", round_mode="round")
     await cocotb.start(Clock(dut.rd_clk, rd_clk_period_ns, units="ns").start())
 
-    almost_full_level = int(dut.ALMOST_FULL_LEVEL.value)
+    almost_full_level = int(dut.AFULLFINAL.value)
 
     await ClockCycles(dut.wr_clk, 3)
 
@@ -150,8 +150,6 @@ async def fifo_rd_wr_test(
     units="ns"
 ) for _ in range(0, 2)]
 
-utils.get_sim_steps(Decimal("8.104"), "ns")
-
 # Factory to automatically generate a set of tests based on the different permutations
 # of the provided test arguments
 tf = TestFactory(fifo_rd_wr_test)