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Remove usize trait impls #364

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Merged
merged 2 commits into from
Mar 28, 2022
Merged

Remove usize trait impls #364

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5bbc76e
Remove usize trait impls
josephlr Mar 28, 2022
bce9ff5
Update bootloader tests
josephlr Mar 28, 2022
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68 changes: 0 additions & 68 deletions src/addr.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -281,23 +281,6 @@ impl AddAssign<u64> for VirtAddr {
}
}

#[cfg(target_pointer_width = "64")]
impl Add<usize> for VirtAddr {
type Output = Self;
#[inline]
fn add(self, rhs: usize) -> Self::Output {
self + rhs as u64
}
}

#[cfg(target_pointer_width = "64")]
impl AddAssign<usize> for VirtAddr {
#[inline]
fn add_assign(&mut self, rhs: usize) {
self.add_assign(rhs as u64)
}
}

impl Sub<u64> for VirtAddr {
type Output = Self;
#[inline]
Expand All @@ -313,23 +296,6 @@ impl SubAssign<u64> for VirtAddr {
}
}

#[cfg(target_pointer_width = "64")]
impl Sub<usize> for VirtAddr {
type Output = Self;
#[inline]
fn sub(self, rhs: usize) -> Self::Output {
self - rhs as u64
}
}

#[cfg(target_pointer_width = "64")]
impl SubAssign<usize> for VirtAddr {
#[inline]
fn sub_assign(&mut self, rhs: usize) {
self.sub_assign(rhs as u64)
}
}

impl Sub<VirtAddr> for VirtAddr {
type Output = u64;
#[inline]
Expand Down Expand Up @@ -564,23 +530,6 @@ impl AddAssign<u64> for PhysAddr {
}
}

#[cfg(target_pointer_width = "64")]
impl Add<usize> for PhysAddr {
type Output = Self;
#[inline]
fn add(self, rhs: usize) -> Self::Output {
self + rhs as u64
}
}

#[cfg(target_pointer_width = "64")]
impl AddAssign<usize> for PhysAddr {
#[inline]
fn add_assign(&mut self, rhs: usize) {
self.add_assign(rhs as u64)
}
}

impl Sub<u64> for PhysAddr {
type Output = Self;
#[inline]
Expand All @@ -596,23 +545,6 @@ impl SubAssign<u64> for PhysAddr {
}
}

#[cfg(target_pointer_width = "64")]
impl Sub<usize> for PhysAddr {
type Output = Self;
#[inline]
fn sub(self, rhs: usize) -> Self::Output {
self - rhs as u64
}
}

#[cfg(target_pointer_width = "64")]
impl SubAssign<usize> for PhysAddr {
#[inline]
fn sub_assign(&mut self, rhs: usize) {
self.sub_assign(rhs as u64)
}
}

impl Sub<PhysAddr> for PhysAddr {
type Output = u64;
#[inline]
Expand Down
2 changes: 1 addition & 1 deletion testing/src/gdt.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ lazy_static! {
static mut STACK: [u8; STACK_SIZE] = [0; STACK_SIZE];

let stack_start = VirtAddr::from_ptr(unsafe { &STACK });
let stack_end = stack_start + STACK_SIZE;
let stack_end = stack_start + STACK_SIZE as u64;
stack_end
};
tss
Expand Down