Added support for AMD verification

Added a custom cpuid file for sde, which enables SSE4a, XOP, TBM and VP2INTERSECT. Fixed `xsave` tests

Author: sayantn

ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile

@@ -10,4 +10,6 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
 
 RUN wget https://downloadmirror.intel.com/813591/sde-external-9.33.0-2024-01-07-lin.tar.xz
 RUN tar -xJf sde-external-9.33.0-2024-01-07-lin.tar.xz
-ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/sde-external-9.33.0-2024-01-07-lin/sde64 -future -rtm-mode full -tsx --"
+ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/sde-external-9.33.0-2024-01-07-lin/sde64 \
+            -cpuid-in /checkout/ci/docker/x86_64-unknown-linux-gnu-emulated/cpuid.def \
+            -rtm-mode full -tsx --"

ci/docker/x86_64-unknown-linux-gnu-emulated/cpuid.def

@@ -0,0 +1,61 @@
+# Copyright (C) 2017-2023 Intel Corporation.
+# 
+# This software and the related documents are Intel copyrighted materials, and your
+# use of them is governed by the express license under which they were provided to
+# you ("License"). Unless the License provides otherwise, you may not use, modify,
+# copy, publish, distribute, disclose or transmit this software or the related
+# documents without Intel's prior written permission.
+# 
+# This software and the related documents are provided as is, with no express or
+# implied warranties, other than those that are expressly stated in the License.
+#
+# CPUID_VERSION = 1.0
+#      Input      =>               Output
+# EAX      ECX    =>   EAX      EBX      ECX      EDX
+00000000 ******** => 00000024 68747541 444d4163 69746e65
+00000001 ******** => 000806f0 00100800 7ffaf3ff bfebfbff
+00000002 ******** => 76035a01 00f0b6ff 00000000 00c10000
+00000003 ******** => 00000000 00000000 00000000 00000000
+00000004 00000000 => 7c004121 01c0003f 0000003f 00000000 #Deterministic Cache
+00000004 00000001 => 7c004122 01c0003f 0000003f 00000000
+00000004 00000002 => 7c004143 03c0003f 000003ff 00000000
+00000004 00000003 => 7c0fc163 0280003f 0000dfff 00000004
+00000004 00000004 => 00000000 00000000 00000000 00000000
+00000005 ******** => 00000040 00000040 00000003 00042120 #MONITOR/MWAIT
+00000006 ******** => 00000077 00000002 00000001 00000000 #Thermal and Power
+00000007 00000000 => 00000001 f3bfbfbf bac05ffe 03d54130 #Extended Features
+00000007 00000001 => 18ee00bf 00000002 00000000 1d29cd3e
+00000008 ******** => 00000000 00000000 00000000 00000000
+00000009 ******** => 00000000 00000000 00000000 00000000 #Direct Cache
+0000000a ******** => 07300403 00000000 00000000 00000603
+0000000b 00000000 => 00000001 00000002 00000100 00000000 #Extended Topology
+0000000b 00000001 => 00000004 00000002 00000201 00000000
+0000000c ******** => 00000000 00000000 00000000 00000000
+0000000d 00000000 => 000e02e7 00002b00 00002b00 00000000 #xcr0
+0000000d 00000001 => 0000001f 00000240 00000100 00000000
+0000000d 00000002 => 00000100 00000240 00000000 00000000
+0000000d 00000005 => 00000040 00000440 00000000 00000000 #zmasks
+0000000d 00000006 => 00000200 00000480 00000000 00000000 #zmmh
+0000000d 00000007 => 00000400 00000680 00000000 00000000 #zmm
+0000000d 00000011 => 00000040 00000ac0 00000002 00000000 #tileconfig
+0000000d 00000012 => 00002000 00000b00 00000006 00000000 #tiles
+0000000d 00000013 => 00000080 000003c0 00000000 00000000 #APX
+00000014 00000000 => 00000000 00000010 00000000 00000000 #ptwrite
+00000019 ******** => 00000000 00000005 00000000 00000000 #Key Locker
+0000001d 00000000 => 00000001 00000000 00000000 00000000 #AMX Tile
+0000001d 00000001 => 04002000 00080040 00000010 00000000 #AMX Palette1
+0000001e ******** => 00000000 00004010 00000000 00000000 #AMX Tmul
+00000024 ******** => 00000000 00070001 00000000 00000000 #AVX10
+80000000 ******** => 80000008 00000000 00000000 00000000
+80000001 ******** => 00000000 00000000 00200961 2c100000
+80000002 ******** => 00000000 00000000 00000000 00000000
+80000003 ******** => 00000000 00000000 00000000 00000000
+80000004 ******** => 00000000 00000000 00000000 00000000
+80000005 ******** => 00000000 00000000 00000000 00000000
+80000006 ******** => 00000000 00000000 01006040 00000000
+80000007 ******** => 00000000 00000000 00000000 00000100
+80000008 ******** => 00003028 00000200 00000200 00000000
+
+# This file was copied from intel-sde/misc/cpuid/future/cpuid.def, and modified to
+# use "AuthenticAMD" as the vendor and the support for `XOP`, `SSE4a`, `TBM` and
+# `AVX512_VP2INTERSECT` was added in the CPUID.

crates/core_arch/src/x86/fxsr.rs

@@ -101,7 +101,7 @@ mod tests {
 
     #[simd_test(enable = "fxsr")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn fxsave() {
+    unsafe fn test_fxsave() {
         let mut a = FxsaveArea::new();
         let mut b = FxsaveArea::new();
 

crates/core_arch/src/x86/mod.rs

@@ -798,15 +798,11 @@ mod bmi2;
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub use self::bmi2::*;
 
-#[cfg(not(stdarch_intel_sde))]
 mod sse4a;
-#[cfg(not(stdarch_intel_sde))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub use self::sse4a::*;
 
-#[cfg(not(stdarch_intel_sde))]
 mod tbm;
-#[cfg(not(stdarch_intel_sde))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub use self::tbm::*;
 

crates/core_arch/src/x86/xsave.rs

@@ -208,11 +208,14 @@ mod tests {
         }
     }
 
-    // FIXME: https://github.com/rust-lang/stdarch/issues/209
-    /*
+    // We cannot test for `_xsave`, `xrstor`, `_xsetbv`, `_xsaveopt`, `_xsaves`, `_xrstors` as they
+    // are privileged instructions and will need access to kernel mode to execute and test them.
+    // see https://github.com/rust-lang/stdarch/issues/209
+
+    #[cfg_attr(stdarch_intel_sde, ignore)]
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn xsave() {
+    unsafe fn test_xsave() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
@@ -222,27 +225,21 @@ mod tests {
         _xsave(b.ptr(), m);
         assert_eq!(a, b);
     }
-    */
 
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn xgetbv_xsetbv() {
+    unsafe fn test_xgetbv() {
         let xcr_n: u32 = _XCR_XFEATURE_ENABLED_MASK;
 
         let xcr: u64 = _xgetbv(xcr_n);
-        // FIXME: XSETBV is a privileged instruction we should only test this
-        // when running in privileged mode:
-        //
-        // _xsetbv(xcr_n, xcr);
         let xcr_cpy: u64 = _xgetbv(xcr_n);
         assert_eq!(xcr, xcr_cpy);
     }
 
-    // FIXME: https://github.com/rust-lang/stdarch/issues/209
-    /*
+    #[cfg_attr(stdarch_intel_sde, ignore)]
     #[simd_test(enable = "xsave,xsaveopt")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn xsaveopt() {
+    unsafe fn test_xsaveopt() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
@@ -252,11 +249,10 @@ mod tests {
         _xsaveopt(b.ptr(), m);
         assert_eq!(a, b);
     }
-    */
 
     #[simd_test(enable = "xsave,xsavec")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn xsavec() {
+    unsafe fn test_xsavec() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
@@ -266,19 +262,4 @@ mod tests {
         _xsavec(b.ptr(), m);
         assert_eq!(a, b);
     }
-
-    // FIXME: https://github.com/rust-lang/stdarch/issues/209
-    /*
-    #[simd_test(enable = "xsave,xsaves")]
-    unsafe fn xsaves() {
-        let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
-        let mut a = XsaveArea::new();
-        let mut b = XsaveArea::new();
-
-        _xsaves(a.ptr(), m);
-        _xrstors(a.ptr(), m);
-        _xsaves(b.ptr(), m);
-        assert_eq!(a, b);
-    }
-    */
 }

crates/core_arch/src/x86_64/fxsr.rs

@@ -101,7 +101,7 @@ mod tests {
 
     #[simd_test(enable = "fxsr")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn fxsave64() {
+    unsafe fn test_fxsave64() {
         let mut a = FxsaveArea::new();
         let mut b = FxsaveArea::new();
 

crates/core_arch/src/x86_64/xsave.rs

@@ -124,16 +124,12 @@ pub unsafe fn _xrstors64(mem_addr: *const u8, rs_mask: u64) {
     xrstors64(mem_addr, (rs_mask >> 32) as u32, rs_mask as u32);
 }
 
-// FIXME: https://github.com/rust-lang/stdarch/issues/209
-// All these tests fail with Intel SDE.
-
 #[cfg(test)]
 mod tests {
     use crate::core_arch::x86_64::xsave;
     use std::fmt;
     use stdarch_test::simd_test;
 
-    // FIXME: https://github.com/rust-lang/stdarch/issues/209
     #[repr(align(64))]
     struct XsaveArea {
         // max size for 256-bit registers is 800 bytes:
@@ -176,10 +172,14 @@ mod tests {
         }
     }
 
-    /*
+    // We cannot test `_xsave64`, `_xrstor64`, `_xsaveopt64`, `_xsaves64` and `_xrstors64` directly
+    // as they are privileged instructions and will need access to the kernel to run and test them.
+    // See https://github.com/rust-lang/stdarch/issues/209
+
+    #[cfg_attr(stdarch_intel_sde, ignore)]
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn xsave64() {
+    unsafe fn test_xsave64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
@@ -190,9 +190,10 @@ mod tests {
         assert_eq!(a, b);
     }
 
+    #[cfg_attr(stdarch_intel_sde, ignore)]
     #[simd_test(enable = "xsave,xsaveopt")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn xsaveopt64() {
+    unsafe fn test_xsaveopt64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
@@ -202,11 +203,10 @@ mod tests {
         xsave::_xsaveopt64(b.ptr(), m);
         assert_eq!(a, b);
     }
-    */
 
     #[simd_test(enable = "xsave,xsavec")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn xsavec64() {
+    unsafe fn test_xsavec64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
@@ -216,18 +216,4 @@ mod tests {
         xsave::_xsavec64(b.ptr(), m);
         assert_eq!(a, b);
     }
-    /*
-       #[simd_test(enable = "xsave,xsaves")]
-       #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-       unsafe fn xsaves64() {
-           let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
-           let mut a = XsaveArea::new();
-           let mut b = XsaveArea::new();
-
-           xsave::_xsaves64(a.ptr(), m);
-           xsave::_xrstors64(a.ptr(), m);
-           xsave::_xsaves64(b.ptr(), m);
-           assert_eq!(a, b);
-       }
-    */
 }

crates/stdarch-verify/tests/x86-intel.rs

@@ -189,25 +189,12 @@ fn verify_all_signatures() {
                 "__cpuid_count",
                 "__cpuid",
                 "__get_cpuid_max",
-                // Priviledged
-                "_xsave",
-                "_xrstor",
+                // Privileged, see https://github.com/rust-lang/stdarch/issues/209
                 "_xsetbv",
-                "_xgetbv",
-                "_xsaveopt",
-                "_xsavec",
                 "_xsaves",
                 "_xrstors",
-                "_xsave64",
-                "_xrstor64",
-                "_xsaveopt64",
-                "_xsavec64",
                 "_xsaves64",
                 "_xrstors64",
-                "_fxsave",
-                "_fxrstor",
-                "_fxsave64",
-                "_fxrstor64",
                 // TSC
                 "_rdtsc",
                 "__rdtscp",
@@ -251,6 +238,10 @@ fn verify_all_signatures() {
                 // Has tests with different name
                 "_mm_min_epi8",
                 "_mm_min_epi32",
+                "_xrstor",
+                "_xrstor64",
+                "_fxrstor",
+                "_fxrstor64",
                 // Needs `f16` to test
                 "_mm_cvtps_ph",
                 "_mm256_cvtps_ph",