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change the default linker of the ARM Cortex-M targets #53648

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Aug 27, 2018
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5 changes: 2 additions & 3 deletions src/librustc_target/spec/thumb_base.rs
Original file line number Diff line number Diff line change
Expand Up @@ -42,9 +42,8 @@ pub fn opts() -> TargetOptions {
// See rust-lang/rfcs#1645 for a discussion about these defaults
TargetOptions {
executables: true,
// In 99%+ of cases, we want to use the `arm-none-eabi-gcc` compiler (there aren't many
// options around)
linker: Some("arm-none-eabi-gcc".to_string()),
// In most cases, LLD is good enough
linker: Some("rust-lld".to_string()),
// Because these devices have very little resources having an unwinder is too onerous so we
// default to "abort" because the "unwind" strategy is very rare.
panic_strategy: PanicStrategy::Abort,
Expand Down
4 changes: 2 additions & 2 deletions src/librustc_target/spec/thumbv6m_none_eabi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@

// Targets the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture)

use spec::{LinkerFlavor, Target, TargetOptions, TargetResult};
use spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
Expand All @@ -23,7 +23,7 @@ pub fn target() -> TargetResult {
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: String::new(),
linker_flavor: LinkerFlavor::Gcc,
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
// The ARMv6-M architecture doesn't support unaligned loads/stores so we disable them
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4 changes: 2 additions & 2 deletions src/librustc_target/spec/thumbv7em_none_eabi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@
// To opt-in to hardware accelerated floating point operations, you can use, for example,
// `-C target-feature=+vfp4` or `-C target-cpu=cortex-m4`.

use spec::{LinkerFlavor, Target, TargetOptions, TargetResult};
use spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
Expand All @@ -32,7 +32,7 @@ pub fn target() -> TargetResult {
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: String::new(),
linker_flavor: LinkerFlavor::Gcc,
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
max_atomic_width: Some(32),
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4 changes: 2 additions & 2 deletions src/librustc_target/spec/thumbv7em_none_eabihf.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
//
// To opt into double precision hardware support, use the `-C target-feature=-fp-only-sp` flag.

use spec::{LinkerFlavor, Target, TargetOptions, TargetResult};
use spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
Expand All @@ -31,7 +31,7 @@ pub fn target() -> TargetResult {
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: String::new(),
linker_flavor: LinkerFlavor::Gcc,
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
// `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the
Expand Down
4 changes: 2 additions & 2 deletions src/librustc_target/spec/thumbv7m_none_eabi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@

// Targets the Cortex-M3 processor (ARMv7-M)

use spec::{LinkerFlavor, Target, TargetOptions, TargetResult};
use spec::{LinkerFlavor, LldFlavor, Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
Expand All @@ -23,7 +23,7 @@ pub fn target() -> TargetResult {
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: String::new(),
linker_flavor: LinkerFlavor::Gcc,
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
max_atomic_width: Some(32),
Expand Down