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‎.github/workflows/riscv-rt.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ jobs:
4242
- name : Build (v-trap)
4343
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=v-trap
4444
- name: Build (all features)
45-
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features
45+
run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode,single-hart,v-trap
4646

4747
# Job to check that all the builds succeeded
4848
build-check:

‎.github/workflows/riscv-semihosting.yaml

+2-2
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ jobs:
1111
build-riscv:
1212
strategy:
1313
matrix:
14-
# All generated code should be running on stable now, MRSV is 1.60.0
15-
toolchain: [ stable, nightly, 1.60.0 ]
14+
# All generated code should be running on stable now, MRSV is 1.61.0
15+
toolchain: [ stable, nightly, 1.61.0 ]
1616
target:
1717
- riscv32i-unknown-none-elf
1818
- riscv32imc-unknown-none-elf

‎.github/workflows/riscv.yaml

+2-2
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ jobs:
1111
build-riscv:
1212
strategy:
1313
matrix:
14-
# All generated code should be running on stable now, MRSV is 1.60.0
15-
toolchain: [ stable, nightly, 1.60.0 ]
14+
# All generated code should be running on stable now, MRSV is 1.61.0
15+
toolchain: [ stable, nightly, 1.61.0 ]
1616
target:
1717
- riscv32i-unknown-none-elf
1818
- riscv32imc-unknown-none-elf

‎riscv-peripheral/Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ license = "ISC"
1616
[dependencies]
1717
embedded-hal = "1.0.0"
1818
embedded-hal-async = { version = "1.0.0", optional = true }
19-
riscv = { path = "../riscv", version = "0.11.1" }
19+
riscv = { path = "../riscv", version = "0.12.0" }
2020
riscv-pac = { path = "../riscv-pac", version = "0.2.0" }
2121

2222
[dev-dependencies]

‎riscv-peripheral/src/aclint.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ pub(crate) mod test {
8787
Err(Error::InvalidVariant(number as usize))
8888
} else {
8989
// SAFETY: valid context number
90-
Ok(unsafe { core::mem::transmute(number) })
90+
Ok(unsafe { core::mem::transmute::<u16, HartId>(number) })
9191
}
9292
}
9393
}

‎riscv-rt/CHANGELOG.md

+5-3
Original file line numberDiff line numberDiff line change
@@ -9,19 +9,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
99

1010
### Added
1111

12+
- Add `no-exceptions` feature to opt-out the default implementation of `_dispatch_exception`
13+
- Add `no-interrupts` feature to opt-out the default implementation of `_dispatch_core_interrupt`
1214
- Add `pre_init_trap` to detect early errors during the boot process.
1315
- Add `v-trap` feature to enable interrupt handling in vectored mode.
1416
- Add `interrupt` proc macro to help defining interrupt handlers.
15-
If `v-trap` feature is enabled, this macro also generates its corresponding trap.
17+
If `v-trap` feature is enabled, this macro also generates its corresponding trap.
1618

1719
### Changed
1820

1921
- Moved all the assembly code to `asm.rs`
2022
- Use `weak` symbols for functions such as `_mp_hook` or `_start_trap`
2123
- `abort` is now `weak`, so it is possible to link third-party libraries including this symbol.
2224
- Made `cfg` variable selection more robust for custom targets
23-
- `_start_trap_rust` now only deals with exceptions. When an interrupt is detected, it now calls
24-
to `_dispatch_interrupt`.
25+
- `_start_trap_rust` now relies on `_dispatch_exception` and `_dispatch_core_interrupt`.
26+
This change allows more flexibility for targets with non-standard exceptions and interrupts.
2527
- Upgrade rust-version to 1.61
2628
- Update `syn` to version 2.0
2729

‎riscv-rt/Cargo.toml

+3-1
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ edition = "2021"
1313
links = "riscv-rt" # Prevent multiple versions of riscv-rt being linked
1414

1515
[dependencies]
16-
riscv = {path = "../riscv", version = "0.11.1"}
16+
riscv = { path = "../riscv", version = "0.12.0" }
1717
riscv-rt-macros = { path = "macros", version = "0.2.1" }
1818

1919
[dev-dependencies]
@@ -23,3 +23,5 @@ panic-halt = "0.2.0"
2323
s-mode = ["riscv-rt-macros/s-mode"]
2424
single-hart = []
2525
v-trap = ["riscv-rt-macros/v-trap"]
26+
no-interrupts = []
27+
no-exceptions = []

‎riscv-rt/macros/Cargo.toml

+1
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ license = "MIT OR Apache-2.0"
1111
name = "riscv-rt-macros"
1212
repository = "https://github.com/rust-embedded/riscv"
1313
version = "0.2.1"
14+
edition = "2021"
1415

1516
[lib]
1617
proc-macro = true

‎riscv-rt/src/asm.rs

-32
Original file line numberDiff line numberDiff line change
@@ -287,38 +287,6 @@ riscv_rt_macros::vectored_interrupt_trap_riscv32!();
287287
#[cfg(all(riscv64, feature = "v-trap"))]
288288
riscv_rt_macros::vectored_interrupt_trap_riscv64!();
289289

290-
#[cfg(feature = "v-trap")]
291-
cfg_global_asm!(
292-
// Set the vector mode to vectored.
293-
r#".section .trap, "ax"
294-
.weak _vector_table
295-
.type _vector_table, @function
296-
297-
.option push
298-
.balign 0x4 // TODO check if this is the correct alignment
299-
.option norelax
300-
.option norvc
301-
302-
_vector_table:
303-
j _start_trap // Interrupt 0 is used for exceptions
304-
j _start_SupervisorSoft_trap
305-
j _start_DefaultHandler_trap // Interrupt 2 is reserved
306-
j _start_MachineSoft_trap
307-
j _start_DefaultHandler_trap // Interrupt 4 is reserved
308-
j _start_SupervisorTimer_trap
309-
j _start_DefaultHandler_trap // Interrupt 6 is reserved
310-
j _start_MachineTimer_trap
311-
j _start_DefaultHandler_trap // Interrupt 8 is reserved
312-
j _start_SupervisorExternal_trap
313-
j _start_DefaultHandler_trap // Interrupt 10 is reserved
314-
j _start_MachineExternal_trap
315-
316-
// default table does not include the remaining interrupts.
317-
// Targets with extra interrupts should override this table.
318-
319-
.option pop"#,
320-
);
321-
322290
#[rustfmt::skip]
323291
global_asm!(
324292
".section .text.abort

‎riscv-rt/src/exceptions.rs

+53
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
use crate::TrapFrame;
2+
3+
extern "C" {
4+
fn InstructionMisaligned(trap_frame: &TrapFrame);
5+
fn InstructionFault(trap_frame: &TrapFrame);
6+
fn IllegalInstruction(trap_frame: &TrapFrame);
7+
fn Breakpoint(trap_frame: &TrapFrame);
8+
fn LoadMisaligned(trap_frame: &TrapFrame);
9+
fn LoadFault(trap_frame: &TrapFrame);
10+
fn StoreMisaligned(trap_frame: &TrapFrame);
11+
fn StoreFault(trap_frame: &TrapFrame);
12+
fn UserEnvCall(trap_frame: &TrapFrame);
13+
fn SupervisorEnvCall(trap_frame: &TrapFrame);
14+
fn MachineEnvCall(trap_frame: &TrapFrame);
15+
fn InstructionPageFault(trap_frame: &TrapFrame);
16+
fn LoadPageFault(trap_frame: &TrapFrame);
17+
fn StorePageFault(trap_frame: &TrapFrame);
18+
fn ExceptionHandler(trap_frame: &TrapFrame);
19+
}
20+
21+
#[doc(hidden)]
22+
#[no_mangle]
23+
pub static __EXCEPTIONS: [Option<unsafe extern "C" fn(&TrapFrame)>; 16] = [
24+
Some(InstructionMisaligned),
25+
Some(InstructionFault),
26+
Some(IllegalInstruction),
27+
Some(Breakpoint),
28+
Some(LoadMisaligned),
29+
Some(LoadFault),
30+
Some(StoreMisaligned),
31+
Some(StoreFault),
32+
Some(UserEnvCall),
33+
Some(SupervisorEnvCall),
34+
None,
35+
Some(MachineEnvCall),
36+
Some(InstructionPageFault),
37+
Some(LoadPageFault),
38+
None,
39+
Some(StorePageFault),
40+
];
41+
42+
#[export_name = "_dispatch_exception"]
43+
#[inline]
44+
unsafe extern "C" fn dispatch_exception(trap_frame: &TrapFrame, code: usize) {
45+
if code < __EXCEPTIONS.len() {
46+
match &__EXCEPTIONS[code] {
47+
Some(handler) => handler(trap_frame),
48+
None => ExceptionHandler(trap_frame),
49+
}
50+
} else {
51+
ExceptionHandler(trap_frame);
52+
}
53+
}

‎riscv-rt/src/interrupts.rs

+67
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
extern "C" {
2+
fn SupervisorSoft();
3+
fn MachineSoft();
4+
fn SupervisorTimer();
5+
fn MachineTimer();
6+
fn SupervisorExternal();
7+
fn MachineExternal();
8+
fn DefaultHandler();
9+
}
10+
11+
#[doc(hidden)]
12+
#[no_mangle]
13+
pub static __CORE_INTERRUPTS: [Option<unsafe extern "C" fn()>; 12] = [
14+
None,
15+
Some(SupervisorSoft),
16+
None,
17+
Some(MachineSoft),
18+
None,
19+
Some(SupervisorTimer),
20+
None,
21+
Some(MachineTimer),
22+
None,
23+
Some(SupervisorExternal),
24+
None,
25+
Some(MachineExternal),
26+
];
27+
28+
#[export_name = "_dispatch_core_interrupt"]
29+
#[inline]
30+
unsafe extern "C" fn dispatch_core_interrupt(code: usize) {
31+
if code < __CORE_INTERRUPTS.len() {
32+
match &__CORE_INTERRUPTS[code] {
33+
Some(handler) => handler(),
34+
None => DefaultHandler(),
35+
}
36+
} else {
37+
DefaultHandler();
38+
}
39+
}
40+
41+
#[cfg(all(riscv, feature = "v-trap"))]
42+
core::arch::global_asm!(
43+
r#" .section .trap, "ax"
44+
.weak _vector_table
45+
.type _vector_table, @function
46+
47+
.option push
48+
.balign 0x4 // TODO check if this is the correct alignment
49+
.option norelax
50+
.option norvc
51+
52+
_vector_table:
53+
j _start_trap // Interrupt 0 is used for exceptions
54+
j _start_SupervisorSoft_trap
55+
j _start_DefaultHandler_trap // Interrupt 2 is reserved
56+
j _start_MachineSoft_trap
57+
j _start_DefaultHandler_trap // Interrupt 4 is reserved
58+
j _start_SupervisorTimer_trap
59+
j _start_DefaultHandler_trap // Interrupt 6 is reserved
60+
j _start_MachineTimer_trap
61+
j _start_DefaultHandler_trap // Interrupt 8 is reserved
62+
j _start_SupervisorExternal_trap
63+
j _start_DefaultHandler_trap // Interrupt 10 is reserved
64+
j _start_MachineExternal_trap
65+
66+
.option pop"#
67+
);

‎riscv-rt/src/lib.rs

+11-101
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,12 @@
460460
#[cfg(riscv)]
461461
mod asm;
462462

463+
#[cfg(not(feature = "no-exceptions"))]
464+
mod exceptions;
465+
466+
#[cfg(not(feature = "no-interrupts"))]
467+
mod interrupts;
468+
463469
#[cfg(feature = "s-mode")]
464470
use riscv::register::scause as xcause;
465471

@@ -519,108 +525,12 @@ pub struct TrapFrame {
519525
#[export_name = "_start_trap_rust"]
520526
pub unsafe extern "C" fn start_trap_rust(trap_frame: *const TrapFrame) {
521527
extern "C" {
522-
fn ExceptionHandler(trap_frame: &TrapFrame);
523-
fn _dispatch_interrupt(code: usize);
528+
fn _dispatch_core_interrupt(code: usize);
529+
fn _dispatch_exception(trap_frame: &TrapFrame, code: usize);
524530
}
525531

526-
let cause = xcause::read();
527-
let code = cause.code();
528-
529-
if cause.is_exception() {
530-
let trap_frame = &*trap_frame;
531-
if code < __EXCEPTIONS.len() {
532-
let h = &__EXCEPTIONS[code];
533-
if let Some(handler) = h {
534-
handler(trap_frame);
535-
} else {
536-
ExceptionHandler(trap_frame);
537-
}
538-
} else {
539-
ExceptionHandler(trap_frame);
540-
}
541-
} else {
542-
_dispatch_interrupt(code);
532+
match xcause::read().cause() {
533+
xcause::Trap::Interrupt(code) => _dispatch_core_interrupt(code),
534+
xcause::Trap::Exception(code) => _dispatch_exception(&*trap_frame, code),
543535
}
544536
}
545-
546-
extern "C" {
547-
fn InstructionMisaligned(trap_frame: &TrapFrame);
548-
fn InstructionFault(trap_frame: &TrapFrame);
549-
fn IllegalInstruction(trap_frame: &TrapFrame);
550-
fn Breakpoint(trap_frame: &TrapFrame);
551-
fn LoadMisaligned(trap_frame: &TrapFrame);
552-
fn LoadFault(trap_frame: &TrapFrame);
553-
fn StoreMisaligned(trap_frame: &TrapFrame);
554-
fn StoreFault(trap_frame: &TrapFrame);
555-
fn UserEnvCall(trap_frame: &TrapFrame);
556-
fn SupervisorEnvCall(trap_frame: &TrapFrame);
557-
fn MachineEnvCall(trap_frame: &TrapFrame);
558-
fn InstructionPageFault(trap_frame: &TrapFrame);
559-
fn LoadPageFault(trap_frame: &TrapFrame);
560-
fn StorePageFault(trap_frame: &TrapFrame);
561-
}
562-
563-
#[doc(hidden)]
564-
#[no_mangle]
565-
pub static __EXCEPTIONS: [Option<unsafe extern "C" fn(&TrapFrame)>; 16] = [
566-
Some(InstructionMisaligned),
567-
Some(InstructionFault),
568-
Some(IllegalInstruction),
569-
Some(Breakpoint),
570-
Some(LoadMisaligned),
571-
Some(LoadFault),
572-
Some(StoreMisaligned),
573-
Some(StoreFault),
574-
Some(UserEnvCall),
575-
Some(SupervisorEnvCall),
576-
None,
577-
Some(MachineEnvCall),
578-
Some(InstructionPageFault),
579-
Some(LoadPageFault),
580-
None,
581-
Some(StorePageFault),
582-
];
583-
584-
#[export_name = "_dispatch_interrupt"]
585-
unsafe extern "C" fn dispatch_interrupt(code: usize) {
586-
extern "C" {
587-
fn DefaultHandler();
588-
}
589-
590-
if code < __INTERRUPTS.len() {
591-
let h = &__INTERRUPTS[code];
592-
if let Some(handler) = h {
593-
handler();
594-
} else {
595-
DefaultHandler();
596-
}
597-
} else {
598-
DefaultHandler();
599-
}
600-
}
601-
602-
extern "C" {
603-
fn SupervisorSoft();
604-
fn MachineSoft();
605-
fn SupervisorTimer();
606-
fn MachineTimer();
607-
fn SupervisorExternal();
608-
fn MachineExternal();
609-
}
610-
611-
#[doc(hidden)]
612-
#[no_mangle]
613-
pub static __INTERRUPTS: [Option<unsafe extern "C" fn()>; 12] = [
614-
None,
615-
Some(SupervisorSoft),
616-
None,
617-
Some(MachineSoft),
618-
None,
619-
Some(SupervisorTimer),
620-
None,
621-
Some(MachineTimer),
622-
None,
623-
Some(SupervisorExternal),
624-
None,
625-
Some(MachineExternal),
626-
];

‎riscv-semihosting/CHANGELOG.md

+1
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ This project adheres to [Semantic Versioning](http://semver.org/).
77

88
### Changed
99

10+
- Bump riscv dependency version
1011
- Made `cfg` variable selection more robust for custom targets
1112
- Fixed debug::exit() on riscv64 QEMU simulation
1213

‎riscv-semihosting/Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,4 @@ default = ["jlink-quirks"]
2424

2525
[dependencies]
2626
critical-section = "1.0.0"
27-
riscv = { path = "../riscv", version = "0.11.0" }
27+
riscv = { path = "../riscv", version = "0.12.0" }

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