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riscv/CHANGELOG.md
@@ -26,6 +26,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Fixed `sip::set_ssoft` and `sip::clear_ssoft` using wrong address
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- Fixed assignment in `mstatus` unit tests.
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+- delay implementation does not use binary labels in inline assembly.
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## [v0.11.1] - 2024-02-15
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riscv/src/asm.rs
@@ -149,9 +149,9 @@ pub fn delay(cycles: u32) {
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() => unsafe {
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let real_cyc = 1 + cycles / 2;
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core::arch::asm!(
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- "1:",
+ "2:",
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"addi {0}, {0}, -1",
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- "bne {0}, zero, 1b",
+ "bne {0}, zero, 2b",
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inout(reg) real_cyc => _,
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options(nomem, nostack),
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)
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