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new store/load functions
1 parent 537c3e7 commit 5f0b9c6

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riscv-rt/macros/src/lib.rs

+14-14
Original file line numberDiff line numberDiff line change
@@ -356,15 +356,14 @@ fn store_trap<T: FnMut(&str) -> bool>(arch: RiscvArch, mut filter: T) -> String
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RiscvArch::Rv32 => (4, "sw"),
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RiscvArch::Rv64 => (8, "sd"),
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};
359-
let mut stores = Vec::new();
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for (i, reg) in TRAP_FRAME
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TRAP_FRAME
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.iter()
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.enumerate()
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.filter(|(_, &reg)| filter(reg))
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{
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stores.push(format!("{store} {reg}, {i}*{width}(sp)"));
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}
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stores.join("\n")
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.map(|(i, reg)| format!("{store} {reg}, {i}*{width}(sp)"))
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.collect::<Vec<_>>()
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.join("\n")
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}
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/// Generate the assembly instructions to load the trap frame.
@@ -374,11 +373,12 @@ fn load_trap(arch: RiscvArch) -> String {
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RiscvArch::Rv32 => (4, "lw"),
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RiscvArch::Rv64 => (8, "ld"),
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};
377-
let mut loads = Vec::new();
378-
for (i, reg) in TRAP_FRAME.iter().enumerate() {
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loads.push(format!("{load} {reg}, {i}*{width}(sp)"));
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}
381-
loads.join("\n")
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TRAP_FRAME
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.iter()
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.enumerate()
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.map(|(i, reg)| format!("{load} {reg}, {i}*{width}(sp)"))
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.collect::<Vec<_>>()
381+
.join("\n")
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}
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384384
/// Generates weak `_start_trap` function in assembly for RISCV-32 targets.
@@ -428,7 +428,7 @@ fn weak_start_trap(arch: RiscvArch) -> TokenStream {
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format!(
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r#"
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core::arch::global_asm!(
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".section .trap, \\"ax\\"
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".section .trap, \"ax\"
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.align {width}
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.weak _start_trap
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_start_trap:
@@ -481,7 +481,7 @@ fn vectored_interrupt_trap(arch: RiscvArch) -> TokenStream {
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let instructions = format!(
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r#"
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core::arch::global_asm!(
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".section .trap, \\"ax\\"
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".section .trap, \"ax\"
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.global _start_DefaultHandler_trap
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_start_DefaultHandler_trap:
@@ -586,7 +586,7 @@ fn start_interrupt_trap(ident: &syn::Ident, arch: RiscvArch) -> proc_macro2::Tok
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let instructions = format!(
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r#"
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core::arch::global_asm!(
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".section .trap, \\"ax\\"
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".section .trap, \"ax\"
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.align 2
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.global _start_{interrupt}_trap
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_start_{interrupt}_trap:

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