Apply suggestions from code review

Co-authored-by: rmsyn <[email protected]>

Author: romancardenas

riscv-rt/macros/src/lib.rs

@@ -426,9 +426,9 @@ fn weak_start_trap(arch: RiscvArch) -> TokenStream {
     let ret = "mret";
 
     format!(
-        "
+        r#"
 core::arch::global_asm!(
-\".section .trap, \\\"ax\\\"
+".section .trap, \\"ax\\"
 .align {width}
 .weak _start_trap
 _start_trap:
@@ -439,7 +439,7 @@ _start_trap:
     {load}
     addi sp, sp, {TRAP_SIZE} * {width}
     {ret}
-\");"
+");"#
     )
     .parse()
     .unwrap()
@@ -479,9 +479,9 @@ fn vectored_interrupt_trap(arch: RiscvArch) -> TokenStream {
     let ret = "mret";
 
     let instructions = format!(
-        "
+        r#"
 core::arch::global_asm!(
-\".section .trap, \\\"ax\\\"
+".section .trap, \\"ax\\"
 
 .global _start_DefaultHandler_trap
 _start_DefaultHandler_trap:
@@ -496,7 +496,7 @@ _continue_interrupt_trap:
     {load}                             // restore trap frame
     addi sp, sp, {TRAP_SIZE} * {width} // deallocate space for trap frame
     {ret}                              // return from interrupt
-\");"
+");"#
     );
 
     instructions.parse().unwrap()
@@ -584,17 +584,17 @@ fn start_interrupt_trap(ident: &syn::Ident, arch: RiscvArch) -> proc_macro2::Tok
     let store = store_trap(arch, |r| r == "a0");
 
     let instructions = format!(
-        "
+        r#"
 core::arch::global_asm!(
-    \".section .trap, \\\"ax\\\"
+    ".section .trap, \\"ax\\"
     .align 2
     .global _start_{interrupt}_trap
     _start_{interrupt}_trap:
         addi sp, sp, -{TRAP_SIZE} * {width} // allocate space for trap frame
         {store}                             // store trap partially (only register a0)
         la a0, {interrupt}                  // load interrupt handler address into a0
         j _continue_interrupt_trap          // jump to common part of interrupt trap
-\");"
+");"#
     );
 
     instructions.parse().unwrap()

riscv-rt/src/asm.rs

@@ -290,7 +290,7 @@ riscv_rt_macros::vectored_interrupt_trap_riscv64!();
 #[cfg(feature = "v-trap")]
 cfg_global_asm!(
     // Set the vector mode to vectored.
-    ".section .trap, \"ax\"
+    r#".section .trap, "ax"
     .weak _vector_table
     .type _vector_table, @function
     
@@ -316,7 +316,7 @@ cfg_global_asm!(
         // default table does not include the remaining interrupts.
         // Targets with extra interrupts should override this table.
     
-    .option pop",
+    .option pop"#,
 );
 
 #[rustfmt::skip]