Merge branch 'master' into vectored-rt

Author: romancardenas

riscv-rt/CHANGELOG.md

@@ -19,6 +19,7 @@ If `v-trap` feature is enabled, this macro also generates its corresponding trap
 - Moved all the assembly code to `asm.rs`
 - Use `weak` symbols for functions such as `_mp_hook` or `_start_trap`
 - `abort` is now `weak`, so it is possible to link third-party libraries including this symbol.
+- Made `cfg` variable selection more robust for custom targets
 - `_start_trap_rust` now only deals with exceptions. When an interrupt is detected, it now calls
 to `_dispatch_interrupt`.
 

riscv-rt/build.rs

@@ -72,14 +72,20 @@ fn parse_target(target: &str, cargo_flags: &str) -> (u32, HashSet<char>) {
 }
 
 fn main() {
+    println!("cargo:rustc-check-cfg=cfg(riscv)");
+    println!("cargo:rustc-check-cfg=cfg(riscv32)");
+    println!("cargo:rustc-check-cfg=cfg(riscv64)");
+    for ext in ['i', 'e', 'm', 'a', 'f', 'd', 'g', 'c'] {
+        println!("cargo:rustc-check-cfg=cfg(riscv{})", ext);
+    }
+
     let target = env::var("TARGET").unwrap();
     let cargo_flags = env::var("CARGO_ENCODED_RUSTFLAGS").unwrap();
     let _name = env::var("CARGO_PKG_NAME").unwrap();
 
     // set configuration flags depending on the target
     if target.starts_with("riscv") {
         println!("cargo:rustc-cfg=riscv");
-
         // This is required until target_arch & target_feature risc-v work is
         // stable and in-use (rust 1.75.0)
         let (bits, extensions) = parse_target(&target, &cargo_flags);

riscv-semihosting/CHANGELOG.md

@@ -5,6 +5,10 @@ This project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Made `cfg` variable selection more robust for custom targets
+
 ## [v0.1.0] - 2023-01-18
 
 - Add recommendation for `semihosting` in README.md.

riscv-semihosting/build.rs

@@ -1,6 +1,8 @@
 use std::env;
 
 fn main() {
+    println!("cargo:rustc-check-cfg=cfg(riscv)");
+
     let target = env::var("TARGET").unwrap();
 
     if target.starts_with("riscv") {

riscv/CHANGELOG.md

@@ -10,7 +10,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Add `Mcause::from(usize)` for use in unit tests
+- Add `Mstatus::from(usize)` for use in unit tests
 - Add `Mstatus.bits()`
+- Add `Eq` and `PartialEq` for `pmpcfgx::{Range, Permission}`
+- Export `riscv::register::macros` module macros for external use
 
 ### Fixed
 
@@ -21,6 +24,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - Made `asm::wfi`, `fence`, `fence_i` and `sfence` safe (ie, removed `unsafe` from their definitions)
+- Made `cfg` variable selection more robust for custom targets
 
 ## [v0.11.0] - 2024-01-14
 

riscv/build.rs

@@ -1,12 +1,16 @@
 use std::env;
 
 fn main() {
-    let target = env::var("TARGET").unwrap();
+    println!("cargo:rustc-check-cfg=cfg(riscv)");
+    println!("cargo:rustc-check-cfg=cfg(riscv32)");
+    println!("cargo:rustc-check-cfg=cfg(riscv64)");
 
-    if target.starts_with("riscv32") {
+    let target_arch = env::var("CARGO_CFG_TARGET_ARCH").unwrap();
+
+    if target_arch == "riscv32" {
         println!("cargo:rustc-cfg=riscv");
         println!("cargo:rustc-cfg=riscv32");
-    } else if target.starts_with("riscv64") {
+    } else if target_arch == "riscv64" {
         println!("cargo:rustc-cfg=riscv");
         println!("cargo:rustc-cfg=riscv64");
     }