Add mtvec-align-{16,64,256} features

Author: ia0

riscv-rt/CHANGELOG.md

@@ -9,7 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
-- Ensure the vector table is 256-byte aligned.
+- Add `mtvec-align-{16,64,256}` features to control the vector table alignment.
 - Ensure the `.heap` section is 4-byte aligned.
 - Limit rustc cfg flags to `riscvi`, `riscvm`, `riscvf`, and `riscvd`.
 - Temporary use of `RISCV_RT_LLVM_ARCH_PATCH` environment variable to include the

riscv-rt/Cargo.toml

@@ -37,3 +37,7 @@ v-trap = ["riscv-rt-macros/v-trap"]
 u-boot = ["riscv-rt-macros/u-boot", "single-hart"]
 no-interrupts = []
 no-exceptions = []
+# Alignment requirement of the vector table in bytes (default is 4).
+mtvec-align-16 = []
+mtvec-align-64 = ["mtvec-align-16"]
+mtvec-align-256 = ["mtvec-align-64"]

riscv-rt/src/asm.rs

@@ -1,24 +1,5 @@
 use core::arch::global_asm;
 
-/// Parse cfg attributes inside a global_asm call.
-macro_rules! cfg_global_asm {
-    {@inner, [$($x:tt)*], } => {
-        global_asm!{$($x)*}
-    };
-    (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
-        #[cfg($meta)]
-        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
-        #[cfg(not($meta))]
-        cfg_global_asm!{@inner, [$($x)*], $($rest)*}
-    };
-    {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
-        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
-    };
-    {$($asms:tt)*} => {
-        cfg_global_asm!{@inner, [], $($asms)*}
-    };
-}
-
 // Provisional patch to avoid LLVM spurious errors when compiling in release mode.
 // This patch is somewhat hardcoded and relies on the fact that the rustc compiler
 // only supports a limited combination of ISA extensions. This patch should be

riscv-rt/src/interrupts.rs

@@ -75,14 +75,20 @@ pub unsafe extern "C" fn _dispatch_core_interrupt(code: usize) {
     any(target_arch = "riscv32", target_arch = "riscv64"),
     feature = "v-trap"
 ))]
-core::arch::global_asm!(
+cfg_global_asm!(
     r#" .section .trap, "ax"
         .weak _vector_table
         .type _vector_table, @function
-        
-        .option push
-        .balign 0x100 // RISC-V requires 4, but implementations may be stricter
-        .option norelax
+        .option push"#,
+    #[cfg(not(feature = "mtvec-align-16"))]
+    ".balign 0x4",
+    #[cfg(all(feature = "mtvec-align-16", not(feature = "mtvec-align-64")))]
+    ".balign 0x10",
+    #[cfg(all(feature = "mtvec-align-64", not(feature = "mtvec-align-256")))]
+    ".balign 0x40",
+    #[cfg(feature = "mtvec-align-256")]
+    ".balign 0x100",
+    r#" .option norelax
         .option norvc
         
         _vector_table:
@@ -99,5 +105,5 @@ core::arch::global_asm!(
             j _start_DefaultHandler_trap      // Interrupt 10 is reserved
             j _start_MachineExternal_trap
         
-        .option pop"#
+        .option pop"#,
 );

riscv-rt/src/lib.rs

@@ -532,6 +532,25 @@
 #![no_std]
 #![deny(missing_docs)]
 
+/// Parse cfg attributes inside a global_asm call.
+macro_rules! cfg_global_asm {
+    {@inner, [$($x:tt)*], } => {
+        core::arch::global_asm!{$($x)*}
+    };
+    (@inner, [$($x:tt)*], #[cfg($meta:meta)] $asm:literal, $($rest:tt)*) => {
+        #[cfg($meta)]
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+        #[cfg(not($meta))]
+        cfg_global_asm!{@inner, [$($x)*], $($rest)*}
+    };
+    {@inner, [$($x:tt)*], $asm:literal, $($rest:tt)*} => {
+        cfg_global_asm!{@inner, [$($x)* $asm,], $($rest)*}
+    };
+    {$($asms:tt)*} => {
+        cfg_global_asm!{@inner, [], $($asms)*}
+    };
+}
+
 #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
 mod asm;