riscv-rt: Align _vector_table to 256 instead of 4

The RISC-V Privileged Specification (version 1.11) for mtvec CSR says:
> The value in the BASE field must always be aligned on a 4-byte boundary, and the MODE setting may
> impose additional alignment constraints on the value in the BASE field.
> [...]
> An implementation may have different alignment constraints for different modes. In particular,
> MODE=Vectored may have stricter alignment constraints than MODE=Direct.

The Ibex Reference Guide for mtvec CSR says[^1]:
> The trap-vector base address, always aligned to 256 bytes

I'm not sure how we can parametrize mtvec alignment without cargo features, so this PR simply uses
the stricter alignment. If a cargo feature is preferred, I can add `mtvec-align-256`. Note that
multiple `mtvec-align-N` features are additive because the stricter one wins.

[^1]: https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#machine-trap-vector-base-address-mtvec

Author: ia0

riscv-rt/CHANGELOG.md

@@ -9,7 +9,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
-- Ensure the `.heap` section is 4-byte aligned
+- Ensure the vector table is 256-byte aligned.
+- Ensure the `.heap` section is 4-byte aligned.
 - Limit rustc cfg flags to `riscvi`, `riscvm`, `riscvf`, and `riscvd`.
 - Temporary use of `RISCV_RT_LLVM_ARCH_PATCH` environment variable to include the
   temporary patch required for avoid LLVM spurious errors.

riscv-rt/src/interrupts.rs

@@ -81,7 +81,7 @@ core::arch::global_asm!(
         .type _vector_table, @function
         
         .option push
-        .balign 0x4 // TODO check if this is the correct alignment
+        .balign 0x100 // RISC-V requires 4, but implementations may be stricter
         .option norelax
         .option norvc