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Add hypervisor register support #41
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Signed-off-by: lingfuyi <[email protected]>
Signed-off-by: lingfuyi <[email protected]>
Signed-off-by: lingfuyi <[email protected]>
Signed-off-by: lingfuyi <[email protected]>
Signed-off-by: lingfuyi <[email protected]>
Signed-off-by: lingfuyi <[email protected]>
src/registers/hdfgwtr_el2.rs
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register_bitfields! {u64, | ||
pub HDFGWTR_EL2 [ | ||
// 63: RES0, 保留位,写0 |
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Is it possible to translate this documentation to English?
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done
- Fix documentation link to point to HDFGWTR_EL2 instead of HDFGRTR_EL2 - Update module description from 'Read Trap' to 'Write Trap' - Update description to mention MSR/MCR writes instead of MRS/MRC reads - Translate Chinese comments to English for consistency Signed-off-by: lingfuyi <[email protected]>
- Fix HAFGRTR_EL2 documentation link to point to correct register - Add missing documentation link for HFGWTR_EL2 - Translate all Chinese comments to English for consistency - Fix documentation describes the correct register types Fixed files: - hafgrtr_el2.rs: Fixed doc link, translated Chinese comments - hdfgrtr_el2.rs: Translated Chinese comments - hfgwtr_el2.rs: Added missing doc link Signed-off-by: lingfuyi <[email protected]>
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Looks good to me. I reviewed the encodings and the fields against a local copy of the Arm ARM.
Hi @andre-richter
Thank you for maintaining this amazing project! This PR introduces a new interface (register HFGRTR_EL2) , This interface is currently being used in my new project [rust for pkvm] to [convert kernel nvhe code to rust].
The changes have been tested with updated test cases (and documentation). If possible, I’d appreciate it if this could be merged to benefit more developers. I’m happy to address any feedback or adjustments needed.
Thank you for your time! 🙏