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Add MECALL backend for RISC-V targets #2473

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Add MECALL backend for RISC-V targets

Add MECALL backend for RISC-V targets #2473

Triggered via pull request February 8, 2025 09:06
@romancardenasromancardenas
synchronize #1017
romancardenas:master
Status Failure
Total duration 9m 58s
Artifacts 3

build.yml

on: pull_request
build docs
1m 21s
build docs
Get modern QEMU, build and store
5m 46s
Get modern QEMU, build and store
Matrix: check examples (esp32c3)
Matrix: check examples (hifive1)
Matrix: check examples (lm3s6965)
Matrix: check (hifive1)
Matrix: check (lm3s6965)
Matrix: clippy (lm3s6965)
Matrix: tests
cargo fmt
16s
cargo fmt
Parse the master branch RTIC version
12s
Parse the master branch RTIC version
build mdbook
52s
build mdbook
Matrix: QEMU run (esp32c3)
Matrix: QEMU run (hifive1)
Matrix: QEMU run (lm3s6965)
ci
0s
ci
Also push branch into release/vX when pushing to master
0s
Also push branch into release/vX when pushing to master
build docs and mdbook for older releases
0s
build docs and mdbook for older releases
deploy
0s
deploy
Publish rtic.rs
0s
Publish rtic.rs
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3 errors
check (hifive1) (riscv32-imac-clint, stable)
Process completed with exit code 1.
check (hifive1) (riscv32-imac-mecall, stable)
The job was canceled because "riscv32-imac-clint_stable" failed.
check (hifive1) (riscv32-imac-mecall, stable)
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
apidocs
39.6 MB
book
41.3 MB
qemu
422 MB