way to clear VSTIP and VSEIP injected by hvip.VSTIP and hvip.VSEIP from VS-mode

[Steven-Li-Xiaogang]

it seems the privilege spec implicit that external interrupt caused pending would have a sperate register named 'E', sip.VSTIP(vsip.VSTIP)/sip.VSEIP(vsip.VSEIP) was called register 'B', and SW only was able to change the status of register 'B' by writing CSR hvip, so it seems that we could not have a way to clear pending status caused hvip.VSTIP/hvip.VSEIP while running at VS-mode.

1. for VS-mode VSTIP, it seems it's not mentioned that hvip.VSTIP is read-only when menvcfg.STCE and henvcfg.STCE are set (mvip.VSTIP is read-only when menvcfg.STCE is set). So how could VS-mode SW get to known it's a interrupt raised by writing hvip.VSTIP or caused by timer (vstimecmp <= time + timedelta). I have found this JIRA How to clear the pending of VS-level timer interrupts which pending is set by hvip.vstip and trap to VS mode? #1589 mentioned to use ecall which makes HS-mode having changes to clear pending by writing hvip.VSTIP, but seems SW have no way to know the interrupt source.
2. for VS-mode VSEIP, pending status of register 'E' is raised by external interrupt controller and MMIO access to claim/clear interrupt from interrupt controller (such as PLIC or IMSIC), which can't clear pending of register 'B' raised from writing hvip.VSEIP, SW also can not recognize it's a virtual interrupt injected by writing hvip.VSEIP or a real external interrupt from controller while they arrived at the same time, so we could not issue an ecall to let HS/M-mode help to clear hvip.VSEIP like what you have mentioned in How to clear the pending of VS-level timer interrupts which pending is set by hvip.vstip and trap to VS mode? #1589