Vector Permutation Design Document #251

govardhnn · 2025-04-06T07:40:37Z

No description provided.

kathlenemagnus-mips · 2025-05-19T16:07:17Z

core/InstArchInfo.hpp

+            COMPRESS,
+            WHOLE_REG_MOVE,
+            UNKNOWN,
+            NONE


NONE should be before UNKNOWN.

kathlenemagnus-mips · 2025-05-19T16:14:30Z

@govardhnn your design doc is missing the critical information that I'm looking for which is "what uops are generated for each type of permutation instruction?". It would be great to include a simple example of uop generation for each type of uop generator that you plan to add.

arches/isa_json/olympia_uarch_rv64v.json

… for NONE

govardhnn · 2025-06-02T18:16:48Z

From today's meeting (2nd June, 2025), the following is the link to my slides with the initial block diagram for the vector slide instructions. Link: Olympia: Vector Permutation Design Proposal <https://docs.google.com/presentation/d/1JPNQCGP9xFT4H0yEiLLE2OtRa35D_gz6fdhwKsWmmy0/edit?usp=sharing> The reference uArch for the other `vcompress` and `vgather` that I presented today is linked below: [Efficient Implementation of RISC-V Vector Permutation Instructions <https://arxiv.org/abs/2505.07112> arXiv:2505.07112 <https://arxiv.org/abs/2505.07112>] - and will be cited in `docs/vector_permutation.adoc` The vector permutation design document PR#251 will also soon be extended based on today's review feedback. Thanks, Govardhan

…

On Mon, May 19, 2025 at 9:47 PM Kathlene Magnus ***@***.***> wrote: ***@***.**** commented on this pull request. ------------------------------ In arches/isa_json/olympia_uarch_rv64v.json <#251 (comment)> : > @@ -104,7 +104,7 @@ { "mnemonic": "vcompress.vm", "pipe": "vpermute", - "uop_gen": "PERMUTE", + "uop_gen": "COMPRESS", This file is generated by gen_uarch_rv64v_json.py so it shouldn't be updated directly. You can modify the Python script and then run it to generate this file. — Reply to this email directly, view it on GitHub <#251 (review)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AI2SKHTVJLPP3PJAAAOTUEL27H7ZBAVCNFSM6AAAAAB2RNA4VSVHI2DSMVQWIX3LMV43YUDVNRWFEZLROVSXG5CSMV3GSZLXHMZDQNJRGM3DCMJTGM> . You are receiving this because you were mentioned.Message ID: ***@***.*** com>

-- Sai Govardhan InCore Semiconductors

klingaard · 2025-07-13T15:08:18Z

Hey @govardhnn where are you with this PR? Specifically, did you address @kathlenemagnus requests? Also, can you get regression to pass again?

govardhnn · 2025-07-19T16:27:48Z

Hi @klingaard and @kathlenemagnus-mips I have been on a personal break for a while - I should have informed the team earlier, apologies..
Can I get back to this by the end of the month? Or please feel free to take this over if the feature is on the critical path.

Thanks,

klingaard · 2025-07-27T19:23:24Z

Hey @govardhnn, yes, please feel free to take the time you need. We do appreciate the contributions that folks make to the model.

klingaard

Preemptive acceptance.

govardhnn · 2025-09-30T17:08:07Z

Hi @klingaard, I will have to discontinue this submission since I have joined a startup in stealth recently. I will be unable to contribute to open source for sometime - and intend to come back in full force once I have the permissions to do so.

I will be happy if any other volunteers would like to build on this vector permutation proposal.

Thanks,
Govardhan

klingaard · 2025-10-04T12:54:02Z

Understood and we do appreciate the contributions you've made! We can take it from here. Best of luck in your endeavors.

govardhnn · 2025-10-05T07:48:39Z

Thanks @klingaard!

kathlenemagnus · 2025-10-13T21:16:15Z

core/vector/VectorUopGenerator.cpp

            &VectorUopGenerator::generateSlideUops_<InstArchInfo::UopGenType::SLIDE1DOWN>);

-        // Vector permute uop generator
+        // Vector general slide uop generators


Would be great if could add some examples for the new uop generators.

kathlenemagnus · 2025-10-13T21:17:28Z

core/vector/VectorUopGenerator.cpp

    }

-    InstPtr VectorUopGenerator::generatePermuteUops_()
+    template <InstArchInfo::UopGenType Type>


Not necessary to have a template parameter if this method is only valid for InstArchInfo::UopGenType::SCALAR_MOVE (according to the static assert on line 512).

kathlenemagnus · 2025-10-13T21:29:32Z

core/vector/VectorUopGenerator.cpp


-    InstPtr VectorUopGenerator::generatePermuteUops_()
+    template <InstArchInfo::UopGenType Type>
+    InstPtr VectorUopGenerator::generateScalarMoveUops_()


I'm not sure I understand what this new generator type provides that isn't already supported. Right now, they are not sequenced at all so no uops are generated and we just send the parent inst down the pipe. If there is a need to generate a uop, we could use the ELEMENTWISE generator and set num_uops_to_generate_ to 1.

kathlenemagnus · 2025-10-13T21:30:54Z

core/vector/VectorUopGenerator.cpp

+        return makeInst_(srcs, dests);
+    }
+
+    template <InstArchInfo::UopGenType Type> InstPtr VectorUopGenerator::generateSlideGeneralUops_()


Again, this generator looks like it's doing the same thing as ELEMENTWISE. Not sure why it is needed.

kathlenemagnus · 2025-10-13T22:04:19Z

@govardhnn This work looks incomplete to me. I would expect this PR to contain modifications to Execute since the uops generated cannot be executed independently of each other.

For example, with your vrgather example in your doc:

UOP 1: vrgather.vv v20, v8, v4   # Process first register group
UOP 2: vrgather.vv v21, v9, v5   # Process second register group
UOP 3: vrgather.vv v22, v10, v6  # Process third register group
UOP 4: vrgather.vv v23, v11, v7  # Process fourth register group

It's possible that the indexes specified in v4 will need to gather elements from multiple vs2 registers (v8-v11) to write the result for v20. UOP 1 on its own will not read the right source registers to be able to write the correct value to v20. The result is that v20 will be marked ready earlier than is functionally possible. I see a similar issue with some of the vslide instructions.

Did you have more work planned for this project that you did not get to? If so, please document it so someone else can continue this work.

kathlenemagnus · 2025-10-13T22:05:58Z

docs/vector_permutation.adoc

+|General slides |`SLIDEUP`/`SLIDEDOWN` |VPERMUTE |4 UOPs
+|Slide1 operations |`SLIDE1UP`/`SLIDE1DOWN` |VINT/VFLOAT |4 UOPs  
+|Register gather |`RGATHER` |VPERMUTE |4 UOPs
+|Vector compress |`COMPRESS` |VPERMUTE |1 (always)


Vector compress always has 1 dest but could have up to 8 vector sources. Is that how you planned to support this instruction type?

govardhnn added 6 commits April 6, 2025 13:09

Add WIP Vector Permutation Design Doc Template

d96a9b2

Add doc on configuring the vector unit - as a intro

8c54e48

Upda te the Vector Permutation instruction list and plan

bf00bb6

Add an example implementation for vector move

39c43fc

Update minor typo

74de265

Update Vector permutation docs and sample impl

cca7b68

kathlenemagnus-mips reviewed May 19, 2025

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arches/isa_json/olympia_uarch_rv64v.json Show resolved Hide resolved

govardhnn and others added 2 commits May 20, 2025 21:45

Update gen_uarch_rv64v_json.py and fix core/InstArchInfo.hpp position…

40833f0

… for NONE

Update Docs with pseudo code

86fe299

govardhnn added 4 commits July 25, 2025 21:43

Add Vector uop generator support for permutation instructions

7409d6e

test/core/

2f9a460

Update the unit block diagram

0be1cff

Update the design doc

c008e48

klingaard approved these changes Jul 27, 2025

View reviewed changes

kathlenemagnus reviewed Oct 13, 2025

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Vector Permutation Design Document #251

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Vector Permutation Design Document #251

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