OpenMIPS

a five stage MIPS CPU write with verilog HDL

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
work		work
OpenMIPS.cr.mti		OpenMIPS.cr.mti
OpenMIPS.mpf		OpenMIPS.mpf
README.md		README.md
ctrl.v		ctrl.v
defines.v		defines.v
div.v		div.v
ex.v		ex.v
ex_mem.v		ex_mem.v
hi_lo.v		hi_lo.v
id.v		id.v
id_ex.v		id_ex.v
if_id.v		if_id.v
mem.v		mem.v
mem_wb.v		mem_wb.v
openmips.v		openmips.v
pc.v		pc.v
regfile.v		regfile.v
rom.v		rom.v
sopc_min.v		sopc_min.v
tb_sopc_min.v		tb_sopc_min.v
test.data		test.data
test.s		test.s
vsim.wlf		vsim.wlf

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