IMX477 Improvements - 6.12 #6798
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Registers 0x0342 / 0x0343 are set via IMX477_REG_LINE_LENGTH as V4L2_CID_HBLANK, so shouldn't be in the register tables. Registers 0x0340 / 0x0341 are set via IMX477_REG_FRAME_LENGTH as V4L2_CID_VBLANK so shouldn't be in the register tables. Registers 0x0112 and 0x0113 set the bit depth, so should be per mode rather than in the common table and overridden for the 10bit mode(s). Signed-off-by: Dave Stevenson <[email protected]>
There are a fair number of registers duplicated in all the mode tables, so move those into the common table. Signed-off-by: Dave Stevenson <[email protected]>
The driver was using a struct v4l2_fract for the min frame time to determine the range for V4L2_CID_VBLANK, and a second to set the default VBLANK value for each mode. However actually the sensor will accept any VBLANK value down to 1 line, and using a struct v4l2_fract to hold the default framerate (which is an integer in all cases) is rather overkill. Drop the minimum frame time, and use a simple integer to set the default. This actually increases the max frame rate in all modes slightly. Signed-off-by: Dave Stevenson <[email protected]>
The register set was always selecting continuous clock mode, even though all our overlays were saying it should be non-continuous. Read the configuration from fwnode and configure the sensor accordingly. Signed-off-by: Dave Stevenson <[email protected]>
Pi5 can support higher CSI2 link frequencies than Pi 0-4, and hence higher framerates. The simplest change is to change the DIV_IOP_PX divider from the current value of 2 to 1 to double the frequency. This is slightly outside the max rate nominally supported by RP1, but seems reliable. Signed-off-by: Dave Stevenson <[email protected]>
The driver can now support a link freq of 900MHz (1.8Gbit/s/lane) for higher frame rates. Add an override for "pi5" that changes this link frequency. Signed-off-by: Dave Stevenson <[email protected]>
For 4k30 recording we want 16:9 output, so add a cropped mode to achieve this. Signed-off-by: Dave Stevenson <[email protected]>
FIXME: Dropping the default frame rate needs to be separated out. Switching between 10 and 12 bit mode only requires a couple of registers to change, and an associated change to the minimum HBLANK that can be supported in the mode based on how long it takes the CSI2 block to send each line of the image. Add suitable switching between the 2 for all modes.
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6.12 version of #6208
Only compile tested.