Done fifo buffer and tests

Author: pConst

read_ahead_buf.sv

@@ -5,15 +5,43 @@
 //------------------------------------------------------------------------------
 
 // INFO ------------------------------------------------------------------------
-// Read ahead buffer
+// Read ahead buffer for FWFT fifo
+//
+// The buffer substitutes fifo read port and performs fifo data update at the
+//   same clock cycle as r_req, combinationally, for a one cycle earlier than
+//   it is expected from standard FWFT fifo
+//
+// Featires:
+//   - effectively increases fifo depth by one word
+//   - adds one cycle lateny for empty flag deassertion
+//   - does not touch fifo write port and full flag operation logic
+//   - hides all combinatorial tinkering inside
+//   - allows controlling and analizing fifo read signals from
+//                             a single always_ff block, like this:
+//
+//             always_ff @(posedge clk) begin
+//
+//                 // read control logic
+//                 if( ~empty ) begin        // masking rd_req in always_ff
+//                   r_req <= 1'b1;
+//                 end else begin
+//                   r_req <= 1'b0;
+//                 end
+//
+//                 // getting input data
+//                 if( r_req ) begin
+//                   new_data[] <= r_data[]; // getting data in always_ff
+//                 end
+//
+//               end
+//             end
 //
-
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
 read_ahead_buf #(
   .DATA_W( 32 )
-)(
+) RB1 (
   .clk(  ),
   .anrst(  ),
 
@@ -30,6 +58,9 @@ read_ahead_buf #(
 
 --- INSTANTIATION TEMPLATE END ---*/
 
+// synopsys translate_off
+`define SIMULATION yes
+// synopsys translate_on
 
 module read_ahead_buf #( parameter
   DATA_W = 32
@@ -48,70 +79,67 @@ module read_ahead_buf #( parameter
   output logic empty
 );
 
-  // buffer initialization flags
-  logic buf_empty = 1'b1;
 
-  // buffer fill request
-  logic buf_fill_req;
-  assign buf_fill_req = ~fifo_empty &&
-                        buf_empty &&
-                        ~buf_fill_req_d1;
+  logic fifo_empty_fall;
+  edge_detect fifo_empty_ed (
+    .clk( clk ),
+    .anrst( anrst ),
+    .in( fifo_empty ),
+    .rising(  ),
+    .falling( fifo_empty_fall ),
+    .both(  )
+  );
+
+  logic fantom_read;
+  logic normal_read;
 
-  // buffer fill and re-fill cycle
-  logic buf_fill_req_d1 = 1'b0;
+  logic buf_empty = 1'b1;
   always_ff @(posedge clk or negedge anrst) begin
     if( ~anrst ) begin
-      buf_fill_req_d1 <= 1'b0;
+      buf_empty = 1'b1;
     end else begin
-      buf_fill_req_d1 <= buf_fill_req;
+      if( fantom_read ) begin
+        buf_empty <= 1'b0;
+      end else if( fifo_empty && r_req ) begin
+        buf_empty = 1'b1;
+      end
     end
   end
 
-  // filtering read requests
-  logic r_req_filt;
-  assign r_req_filt = anrst &&
-                      ~fifo_empty &&
-                      ~buf_empty &&
-                      ~buf_fill_req && r_req;
+  assign fantom_read = fifo_empty_fall && buf_empty;
 
-  logic r_req_rise;
-  logic r_req_fall;
-  edge_detect r_req_ed (
-    .clk( clk ),
-    .nrst( anrst ),
-    .in( r_req_filt ),
-    .rising( r_req_rise ),
-    .falling( r_req_fall ),
-    .both(  )
-  );
+  assign normal_read = r_req && ~fifo_empty;
 
-  assign fifo_r_req = r_req_filt;
-  assign empty = anrst && fifo_empty && buf_empty;
+  assign empty = buf_empty ||            // empty falls only after fantom read
+                 (r_req && fifo_empty);  // early empty assertion
 
-  // buffer itself
-  logic [DATA_W-1:0] r_data_buf = '0;
-  always_ff @(posedge clk or negedge anrst) begin
-    if( ~anrst ) begin
-      buf_empty = 1'b1;
-    end else begin
+  assign fifo_r_req = anrst &&
+                      (fantom_read || normal_read);
 
-      if( buf_fill_req_d1 ) begin
-        r_data_buf[DATA_W-1:0] <= fifo_r_data[DATA_W-1:0];
-        buf_empty = 1'b0;
-      end else if( ~r_req_filt && r_req_fall )  begin
-        r_data_buf[DATA_W-1:0] <= fifo_r_data[DATA_W-1:0];
-      end
+  // prepare combinational signal for soft_latch
+  logic latch_req;
+  logic [DATA_W-1:0] r_data_latch;
+  always_comb begin
+    latch_req = (fantom_read || normal_read) ||
+                ( fifo_empty && r_req );        // buffer depletion
 
+    if( ( fantom_read || normal_read ) ||
+        ( fifo_empty && r_req ) ) begin
+      r_data_latch[DATA_W-1:0] = fifo_r_data[DATA_W-1:0];
+    //end else if( fifo_empty && r_req ) begin  // buffer depletion
+    //  r_data_latch[DATA_W-1:0] = '0;
+    end else begin
+      r_data_latch[DATA_W-1:0] = '0;
     end
   end
 
   soft_latch #(
     .WIDTH( DATA_W )
-  ) r_data_latch (
+  ) r_data_latch_b (
     .clk( clk ),
     .anrst( anrst ),
-    .latch( r_req_filt ),
-    .in( (r_req_rise)?(r_data_buf[DATA_W-1:0]):(fifo_r_data[DATA_W-1:0]) ),
+    .latch( latch_req ),
+    .in( r_data_latch[DATA_W-1:0] ),
     .out( r_data[DATA_W-1:0] )
   );