Minor style fixes

Author: pConst

clk_divider.sv

@@ -1,11 +1,12 @@
 //------------------------------------------------------------------------------
 // clk_divider.sv
+// published as part of https://github.com/pConst/basic_verilog
 // Konstantin Pavlov, [email protected]
 //------------------------------------------------------------------------------
 
 // INFO ------------------------------------------------------------------------
 //  Divides main clock to get derivative slower synchronous clocks
-
+//
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 
@@ -27,13 +28,13 @@ module clk_divider #( parameter
   input clk,
   input nrst,
   input ena,
-  output logic [(WIDTH-1):0] out = 0
+  output logic [(WIDTH-1):0] out = '0
 );
 
 
 always_ff @(posedge clk) begin
   if ( ~nrst ) begin
-    out[(WIDTH-1):0] <= 0;
+    out[(WIDTH-1):0] <= '0;
   end else if (ena) begin
     out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
   end

delay.sv

@@ -1,5 +1,6 @@
 //------------------------------------------------------------------------------
-// delay.v
+// delay.sv
+// published as part of https://github.com/pConst/basic_verilog
 // Konstantin Pavlov, [email protected]
 //------------------------------------------------------------------------------
 
@@ -12,16 +13,15 @@
 // Tip for Xilinx-based implementations: Leave nrst=1'b1 and ena=1'b1 on
 // purpose of inferring Xilinx`s SRL16E/SRL32E primitives
 //
-//
 // CAUTION: delay module is widely used for synchronizing signals across clock
 //   domains. When synchronizing, please exclude input data paths from timing
-//   analisys manually by writing appropriate set_false_path SDC constraint
+//   analysis manually by writing appropriate set_false_path SDC constraint
 //
 // Version 2 introduces "ALTERA_BLOCK_RAM" option to implement delays using
-//   block RAM. Quartus can make shifters on block RAM aautomatically
+//   block RAM. Quartus can make shifters on block RAM automatically
 //   using 'altshift_taps' internal module when "Auto Shift Register
 //   Replacement" option is ON
-
+//
 
 /* --- INSTANTIATION TEMPLATE BEGIN ---
 

dynamic_delay.sv

@@ -1,5 +1,6 @@
 //--------------------------------------------------------------------------------
-// dynamic_delay.v
+// dynamic_delay.sv
+// published as part of https://github.com/pConst/basic_verilog
 // Konstantin Pavlov, [email protected]
 //--------------------------------------------------------------------------------
 

soft_latch.sv

@@ -81,8 +81,6 @@ always_comb begin
   end else begin
     out[WIDTH-1:0] <= in_buf[WIDTH-1:0];
   end
-
-
 end
 
 endmodule