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Konstantin Pavlov
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Updated dynamic_delay to allow delays bit-wize, not just element-wize
1 parent 431d061 commit 3474f7b

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7 files changed

+328
-24
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7 files changed

+328
-24
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‎dynamic_delay.sv

100644100755
+49-24
Original file line numberDiff line numberDiff line change
@@ -4,55 +4,80 @@
44
//--------------------------------------------------------------------------------
55

66
// INFO --------------------------------------------------------------------------------
7-
// Dynamic delay for arbitrary signal
7+
// Dynamic delay for arbitrary signal.
88
//
9-
// CAUTION: The module intentionally does NOT implement error handling when
10-
// LENGTH is not a multiple of 2. Please handle "out of range"
11-
// checks externally.
9+
// Incoming data elements have WIDTH bits each. Module does serialization of
10+
// input data and outputs flattened bits, based on provided selector value.
11+
// You can perform delays bit-wize, not just element-wize.
12+
//
13+
// CAUTION: Be careful selecting last, most-delayed "WIDTH" number of bits.
14+
// The module intentionally does NOT implement "out of range"
15+
// checks. Please handle them externally.
16+
1217

1318

1419
/* --- INSTANTIATION TEMPLATE BEGIN ---
1520
1621
dynamic_delay #(
17-
.LENGTH( 8 )
18-
//.SEL_W( 3 )
19-
) DD1 (
22+
.LENGTH( 3 ),
23+
.WIDTH( 4 )
24+
) M (
2025
.clk( clk ),
21-
.nrst( 1'b1 ),
26+
.nrst( nrst ),
2227
.ena( 1'b1 ),
23-
.in( ),
24-
.sel( ),
25-
.out( )
28+
.in( in_data[3:0] ),
29+
.sel( sel[3:0] ),
30+
.out( out_data[3:0] )
2631
);
2732
2833
--- INSTANTIATION TEMPLATE END ---*/
2934

3035

3136
module dynamic_delay #( parameter
32-
LENGTH = 8, // maximum delay chain width
33-
SEL_W = $clog2(LENGTH) // output selector width
37+
LENGTH = 63, // maximum delay chain length
38+
WIDTH = 4, // data width
39+
40+
SEL_W = $clog2( (LENGTH+1)*WIDTH ) // output selector width
41+
// plus one is for zero delay element
3442
)(
3543
input clk,
3644
input nrst,
3745
input ena,
38-
input in,
39-
input [SEL_W-1:0] sel, // output selector
40-
output logic out
46+
input [WIDTH-1:0] in, // input data
47+
input [SEL_W-1:0] sel, // output selector
48+
output logic [WIDTH-1:0] out // output data
4149
);
4250

43-
logic [(LENGTH-1):0] data = 0;
51+
52+
53+
logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;
54+
55+
// packed vector includes extra bits
56+
logic [(LENGTH+1)*WIDTH-1:0] pack_data;
57+
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;
4458

4559
integer i;
4660
always_ff @(posedge clk) begin
47-
if (~nrst) begin
48-
data[(LENGTH-1):0] <= 0;
49-
out <= 0;
61+
if( ~nrst ) begin
62+
// reset all data except zero element
63+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
64+
data[i][WIDTH-1:0] <= '0;
65+
end
5066
end else if (ena) begin
51-
data[0] <= in;
52-
for (i=1; i<LENGTH; i=i+1) begin
53-
data[i] <= data[i-1];
67+
for( i=1; i<(LENGTH+1); i=i+1 ) begin
68+
data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
5469
end
55-
out <= data[sel[SEL_W-1:0]];
70+
end
71+
end
72+
73+
integer j;
74+
always_comb begin
75+
// zero element assignment
76+
data[0][WIDTH-1:0] <= in[WIDTH-1:0];
77+
78+
// output selector, sel==0 gives non-delayed output
79+
for( j=0; j<WIDTH; j=j+1 ) begin
80+
out[j] <= pack_data[sel[SEL_W-1:0]+j];
5681
end
5782
end
5883

‎dynamic_delay_tb/c_rand.v

+48
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@@ -0,0 +1,48 @@
1+
// Copyright 2007 Altera Corporation. All rights reserved.
2+
// Altera products are protected under numerous U.S. and foreign patents,
3+
// maskwork rights, copyrights and other intellectual property laws.
4+
//
5+
// This reference design file, and your use thereof, is subject to and governed
6+
// by the terms and conditions of the applicable Altera Reference Design
7+
// License Agreement (either as signed by you or found at www.altera.com). By
8+
// using this reference design file, you indicate your acceptance of such terms
9+
// and conditions between you and Altera Corporation. In the event that you do
10+
// not agree with such terms and conditions, you may not use the reference
11+
// design file and please promptly destroy any copies you have made.
12+
//
13+
// This reference design file is being provided on an "as-is" basis and as an
14+
// accommodation and therefore all warranties, representations or guarantees of
15+
// any kind (whether express, implied or statutory) including, without
16+
// limitation, warranties of merchantability, non-infringement, or fitness for
17+
// a particular purpose, are specifically disclaimed. By making this reference
18+
// design file available, Altera expressly does not recommend, suggest or
19+
// require that this reference design file be used in combination with any
20+
// other product not provided by Altera.
21+
/////////////////////////////////////////////////////////////////////////////
22+
23+
// C runtime library random number generator
24+
//
25+
// uses 32 logic cells for DFF/ADD and 8 DSP blocks for the
26+
// 32x18=>32 multiply
27+
28+
module c_rand (clk,rst,reseed,seed_val,out);
29+
input clk,rst,reseed;
30+
input [31:0] seed_val;
31+
output [15:0] out;
32+
wire [15:0] out;
33+
34+
reg [31:0] state;
35+
36+
always @(posedge clk or posedge rst) begin
37+
if (rst) state <= 0;
38+
else begin
39+
if (reseed) state <= seed_val;
40+
else begin
41+
state <= state * 32'h343fd + 32'h269EC3;
42+
end
43+
end
44+
end
45+
46+
assign out = (state >> 16) & 16'h7fff;
47+
48+
endmodule

‎dynamic_delay_tb/compile.bat

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1+
modelsim.exe -do compile.tcl

‎dynamic_delay_tb/compile.sh

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1+
#!/bin/bash
2+
3+
# compile.sh
4+
# Konstantin Pavlov, [email protected]
5+
#
6+
# This is a support script for launching "Modelsim compile script" on Linux
7+
8+
9+
vsim -do compile.tcl

‎dynamic_delay_tb/compile.tcl

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1+
#------------------------------------------------------------------------------
2+
# compile.tcl
3+
# Konstantin Pavlov, [email protected]
4+
#------------------------------------------------------------------------------
5+
6+
# INFO ------------------------------------------------------------------------
7+
# Modelsim compile script
8+
# based on "ModelSimSE general compile script version 1.1" by Doulos
9+
10+
# launch the script by "vsim -do compile.tcl" command on linux
11+
# or by "modelsim.exe -do compile.tcl" on windows
12+
13+
14+
# Simply change the project settings in this section
15+
# for each new project. There should be no need to
16+
# modify the rest of the script.
17+
set library_file_list {
18+
19+
work {dynamic_delay_tb.sv
20+
../dynamic_delay.sv
21+
c_rand.v
22+
../edge_detect.sv
23+
../delay.sv
24+
../clk_divider.sv}
25+
}
26+
27+
set vsim_params "-L altera_mf_ver -L altera_mf -L lpm_ver -L lpm"
28+
29+
set top_level work.dynamic_delay_tb
30+
31+
# Console commands:
32+
# r = Recompile changed and dependent files
33+
# rr = Recompile everything
34+
# q = Quit without confirmation
35+
36+
# After sourcing the script from ModelSim for the
37+
# first time use these commands to recompile.
38+
proc r {} {uplevel #0 source compile.tcl}
39+
proc rr {} {global last_compile_time
40+
set last_compile_time 0
41+
r }
42+
proc q {} {quit -force }
43+
44+
#Does this installation support Tk?
45+
set tk_ok 1
46+
if [catch {package require Tk}] {set tk_ok 0}
47+
48+
# Prefer a fixed point font for the transcript
49+
set PrefMain(font) {Courier 10 roman normal}
50+
51+
# Compile out of date files
52+
set time_now [clock seconds]
53+
if [catch {set last_compile_time}] {
54+
set last_compile_time 0
55+
}
56+
foreach {library file_list} $library_file_list {
57+
vlib $library
58+
vmap work $library
59+
foreach file $file_list {
60+
if { $last_compile_time < [file mtime $file] } {
61+
if [regexp {.vhdl?$} $file] {
62+
vcom -93 $file
63+
} else {
64+
vlog $file
65+
}
66+
set last_compile_time 0
67+
}
68+
}
69+
}
70+
set last_compile_time $time_now
71+
72+
# Load the simulation
73+
eval vsim $top_level $vsim_params
74+
75+
# Load saved wave patterns
76+
do wave.do
77+
78+
# Run the simulation
79+
run 100us
80+
81+
wave zoom range 0 100us
82+
83+
# How long since project began?
84+
if {[file isfile start_time.txt] == 0} {
85+
set f [open start_time.txt w]
86+
puts $f "Start time was [clock seconds]"
87+
close $f
88+
} else {
89+
set f [open start_time.txt r]
90+
set line [gets $f]
91+
close $f
92+
regexp {\d+} $line start_time
93+
set total_time [expr ([clock seconds]-$start_time)/60]
94+
puts "Project time is $total_time minutes"
95+
}
96+

‎dynamic_delay_tb/dynamic_delay_tb.sv

+95
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@@ -0,0 +1,95 @@
1+
2+
// testbench for dynamic_delay_tb.sv module
3+
4+
`timescale 1ns / 1ps
5+
6+
module dynamic_delay_tb();
7+
8+
logic clk200;
9+
initial begin
10+
#0 clk200 = 1'b0;
11+
forever
12+
#2.5 clk200 = ~clk200;
13+
end
14+
15+
logic rst;
16+
initial begin
17+
#0 rst = 1'b0;
18+
#10.2 rst = 1'b1;
19+
#5 rst = 1'b0;
20+
end
21+
22+
logic nrst;
23+
assign nrst = ~rst;
24+
25+
logic rst_once;
26+
initial begin
27+
#0 rst_once = 1'b0;
28+
#10.2 rst_once = 1'b1;
29+
#5 rst_once = 1'b0;
30+
end
31+
32+
logic nrst_once;
33+
assign nrst_once = ~rst_once;
34+
35+
logic [31:0] DerivedClocks;
36+
clk_divider #(
37+
.WIDTH( 32 )
38+
) cd1 (
39+
.clk( clk200 ),
40+
.nrst( nrst_once ),
41+
.ena( 1'b1 ),
42+
.out( DerivedClocks[31:0] )
43+
);
44+
45+
logic [31:0] E_DerivedClocks;
46+
edge_detect ed1[31:0] (
47+
.clk( {32{clk200}} ),
48+
.nrst( {32{nrst_once}} ),
49+
.in( DerivedClocks[31:0] ),
50+
.rising( E_DerivedClocks[31:0] ),
51+
.falling( ),
52+
.both( )
53+
);
54+
55+
logic [15:0] RandomNumber1;
56+
c_rand rng1 (
57+
.clk( clk200 ),
58+
.rst( rst_once ),
59+
.reseed( 1'b0 ),
60+
.seed_val( DerivedClocks[31:0] ),
61+
.out( RandomNumber1[15:0] )
62+
);
63+
64+
65+
// Module under test ==========================================================
66+
67+
logic [5:0] test_data = '0;
68+
logic [3:0] sel = '0;
69+
always_ff @(posedge clk200) begin
70+
if( ~nrst_once ) begin
71+
test_data[5:0] <= '0;
72+
sel[3:0] <= '0;
73+
end else begin
74+
test_data[5:0] <= test_data[5:0] + 1'b1;
75+
if( test_data[5:0]=='1 ) begin
76+
sel[3:0] <= sel[3:0] + 1'b1;
77+
end
78+
end
79+
end
80+
81+
82+
dynamic_delay #(
83+
.LENGTH( 3 ),
84+
.WIDTH( 4 )
85+
) M (
86+
.clk( clk200 ),
87+
.nrst( nrst_once ),
88+
.ena( 1'b1 ),
89+
.in( test_data[3:0] ),
90+
.sel( sel[3:0] ),
91+
.out( )
92+
);
93+
94+
95+
endmodule

‎dynamic_delay_tb/wave.do

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1+
onerror {resume}
2+
quietly WaveActivateNextPane {} 0
3+
add wave -noupdate /dynamic_delay_tb/M/LENGTH
4+
add wave -noupdate /dynamic_delay_tb/M/WIDTH
5+
add wave -noupdate /dynamic_delay_tb/M/SEL_W
6+
add wave -noupdate /dynamic_delay_tb/M/clk
7+
add wave -noupdate /dynamic_delay_tb/M/nrst
8+
add wave -noupdate /dynamic_delay_tb/M/ena
9+
add wave -noupdate -radix hexadecimal -childformat {{{/dynamic_delay_tb/M/in[3]} -radix hexadecimal} {{/dynamic_delay_tb/M/in[2]} -radix hexadecimal} {{/dynamic_delay_tb/M/in[1]} -radix hexadecimal} {{/dynamic_delay_tb/M/in[0]} -radix hexadecimal}} -expand -subitemconfig {{/dynamic_delay_tb/M/in[3]} {-radix hexadecimal} {/dynamic_delay_tb/M/in[2]} {-radix hexadecimal} {/dynamic_delay_tb/M/in[1]} {-radix hexadecimal} {/dynamic_delay_tb/M/in[0]} {-radix hexadecimal}} /dynamic_delay_tb/M/in
10+
add wave -noupdate -radix hexadecimal /dynamic_delay_tb/M/sel
11+
add wave -noupdate -radix hexadecimal -childformat {{{/dynamic_delay_tb/M/out[3]} -radix hexadecimal} {{/dynamic_delay_tb/M/out[2]} -radix hexadecimal} {{/dynamic_delay_tb/M/out[1]} -radix hexadecimal} {{/dynamic_delay_tb/M/out[0]} -radix hexadecimal}} -subitemconfig {{/dynamic_delay_tb/M/out[3]} {-radix hexadecimal} {/dynamic_delay_tb/M/out[2]} {-radix hexadecimal} {/dynamic_delay_tb/M/out[1]} {-radix hexadecimal} {/dynamic_delay_tb/M/out[0]} {-radix hexadecimal}} /dynamic_delay_tb/M/out
12+
add wave -noupdate -radix hexadecimal /dynamic_delay_tb/M/data
13+
TreeUpdate [SetDefaultTree]
14+
WaveRestoreCursors {{Cursor 1} {1330926 ps} 0}
15+
quietly wave cursor active 1
16+
configure wave -namecolwidth 209
17+
configure wave -valuecolwidth 100
18+
configure wave -justifyvalue right
19+
configure wave -signalnamewidth 0
20+
configure wave -snapdistance 10
21+
configure wave -datasetprefix 0
22+
configure wave -rowmargin 4
23+
configure wave -childrowmargin 2
24+
configure wave -gridoffset 0
25+
configure wave -gridperiod 1
26+
configure wave -griddelta 40
27+
configure wave -timeline 0
28+
configure wave -timelineunits ns
29+
update
30+
WaveRestoreZoom {3620021 ps} {5306117 ps}

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