Added SIMULATION define to the testbench template

Author: pConst

delay.sv

@@ -1,5 +1,5 @@
 //------------------------------------------------------------------------------
-// delay.v
+// delay.sv
 // Konstantin Pavlov, [email protected]
 //------------------------------------------------------------------------------
 

main_tb.sv

@@ -6,6 +6,9 @@
 // INFO ------------------------------------------------------------------------
 // Testbench template with basic clocking, reset and random stimulus signals
 
+// use this define to make some things differently in simulation
+`define SIMULATION yes
+
 `timescale 1ns / 1ps
 
 module main_tb();