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Konstantin Pavlov
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Added module to switch dims in a 2D systemverilog array
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‎reverse_dimensions.sv

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//------------------------------------------------------------------------------
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// reverse_dimensions.sv
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// "Physically" reverses dimension order in systemv_erilog 2D vector
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// Thus in[7][1] signal becomes out[1][7], in[6][10] becomes out[10][6] and vise-versa
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// Module is no doubt synthesizable, but its instance does NOT occupy any FPGA resources!
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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reverse_dimensions #(
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.D1_WIDTH( 8 ),
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.D2_WIDTH( 3 )
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) RD1 (
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.in( smth[7:0][2:0] ),
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.out( htms[2:0][7:0] ) // reversed bit order
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module reverse_dimensions #( parameter
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D1_WIDTH = 8, // first dimention width
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D2_WIDTH = 3 // second dimention width
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)(
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input [D1_WIDTH-1:0][D2_WIDTH-1:0] in,
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output logic [D2_WIDTH-1:0][D1_WIDTH-1:0] out
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);
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genvar i;
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genvar j;
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generate
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for (i = 0; i < D1_WIDTH ; i++) begin : gen_i
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for (j = 0; j < D2_WIDTH ; j++) begin : gen_j
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always_comb begin
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out[j][i] = in[i][j];
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end // always_comb
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end // for
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end // for
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endgenerate
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endmodule

‎reverse_dimensions_tb/c_rand.v

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// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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// This reference design file, and your use thereof, is subject to and governed
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// by the terms and conditions of the applicable Altera Reference Design
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// License Agreement (either as signed by you or found at www.altera.com). By
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// using this reference design file, you indicate your acceptance of such terms
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// and conditions between you and Altera Corporation. In the event that you do
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// not agree with such terms and conditions, you may not use the reference
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// design file and please promptly destroy any copies you have made.
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//
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// This reference design file is being provided on an "as-is" basis and as an
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// accommodation and therefore all warranties, representations or guarantees of
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// any kind (whether express, implied or statutory) including, without
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// limitation, warranties of merchantability, non-infringement, or fitness for
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// a particular purpose, are specifically disclaimed. By making this reference
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// design file available, Altera expressly does not recommend, suggest or
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// require that this reference design file be used in combination with any
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// other product not provided by Altera.
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/////////////////////////////////////////////////////////////////////////////
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// C runtime library random number generator
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//
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// uses 32 logic cells for DFF/ADD and 8 DSP blocks for the
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// 32x18=>32 multiply
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module c_rand (clk,rst,reseed,seed_val,out);
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input clk,rst,reseed;
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input [31:0] seed_val;
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output [15:0] out;
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wire [15:0] out;
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reg [31:0] state;
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always @(posedge clk or posedge rst) begin
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if (rst) state <= 0;
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else begin
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if (reseed) state <= seed_val;
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else begin
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state <= state * 32'h343fd + 32'h269EC3;
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end
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end
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end
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assign out = (state >> 16) & 16'h7fff;
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endmodule

‎reverse_dimensions_tb/compile.bat

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modelsim.exe -do compile.tcl

‎reverse_dimensions_tb/compile.sh

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#!/bin/bash
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# compile.sh
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# Konstantin Pavlov, [email protected]
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#
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# This is a support script for launching "Modelsim compile script" on Linux
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vsim -do compile.tcl

‎reverse_dimensions_tb/compile.tcl

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#------------------------------------------------------------------------------
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# compile.tcl
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# Konstantin Pavlov, [email protected]
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# Modelsim compile script
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# based on "ModelSimSE general compile script version 1.1" by Doulos
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# launch the script by "vsim -do compile.tcl" command on linux
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# or by "modelsim.exe -do compile.tcl" on windows
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# Simply change the project settings in this section
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# for each new project. There should be no need to
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# modify the rest of the script.
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set library_file_list {
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work {reverse_dimensions_tb.sv
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../reverse_dimensions.sv
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c_rand.v
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../edge_detect.sv
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../clk_divider.sv}
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}
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set vsim_params "-L altera_mf_ver -L altera_mf -L lpm_ver -L lpm"
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set top_level work.reverse_dimensions_tb
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# Console commands:
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# r = Recompile changed and dependent files
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# rr = Recompile everything
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# q = Quit without confirmation
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# After sourcing the script from ModelSim for the
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# first time use these commands to recompile.
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proc r {} {uplevel #0 source compile.tcl}
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proc rr {} {global last_compile_time
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set last_compile_time 0
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r }
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proc q {} {quit -force }
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#Does this installation support Tk?
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set tk_ok 1
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if [catch {package require Tk}] {set tk_ok 0}
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# Prefer a fixed point font for the transcript
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set PrefMain(font) {Courier 10 roman normal}
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# Compile out of date files
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set time_now [clock seconds]
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if [catch {set last_compile_time}] {
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set last_compile_time 0
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}
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foreach {library file_list} $library_file_list {
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vlib $library
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vmap work $library
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foreach file $file_list {
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if { $last_compile_time < [file mtime $file] } {
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if [regexp {.vhdl?$} $file] {
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vcom -93 $file
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} else {
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vlog -sv $file
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}
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set last_compile_time 0
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}
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}
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}
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set last_compile_time $time_now
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# Load the simulation
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eval vsim $top_level $vsim_params
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# Load saved wave patterns
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do wave.do
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# Run the simulation
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run 100us
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wave zoom range 0 100us
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# How long since project began?
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if {[file isfile start_time.txt] == 0} {
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set f [open start_time.txt w]
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puts $f "Start time was [clock seconds]"
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close $f
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} else {
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set f [open start_time.txt r]
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set line [gets $f]
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close $f
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regexp {\d+} $line start_time
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set total_time [expr ([clock seconds]-$start_time)/60]
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puts "Project time is $total_time minutes"
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}
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‎reverse_dimensions_tb/reverse_dimensions_tb.sv

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//------------------------------------------------------------------------------
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// reverse_dimensions_tb.sv
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// testbench for reverse_dimensions module
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`timescale 1ns / 1ps
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module reverse_dimensions_tb();
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logic clk200;
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initial begin
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#0 clk200 = 1;
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forever
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#2.5 clk200 = ~clk200;
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end
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logic rst;
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initial begin
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#10.2 rst = 1;
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#5 rst = 0;
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//#10000;
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forever begin
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#9985 rst = ~rst;
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#5 rst = ~rst;
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end
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end
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logic nrst;
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assign nrst = ~rst;
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logic rst_once;
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initial begin // initializing non-X data before PLL starts
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#10.2 rst_once = 1;
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#5 rst_once = 0;
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end
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initial begin
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#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
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#5 rst_once = 0;
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end
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logic nrst_once;
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assign nrst_once = ~rst_once;
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logic [31:0] DerivedClocks;
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clk_divider #(
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.WIDTH( 32 )
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) CD1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.ena( 1'b1 ),
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.out( DerivedClocks[31:0] )
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);
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logic [31:0] E_DerivedClocks;
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edge_detect ED1[31:0] (
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.clk( {32{clk200}} ),
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.nrst( {32{nrst_once}} ),
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.in( DerivedClocks[31:0] ),
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.rising( E_DerivedClocks[31:0] ),
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.falling( ),
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.both( )
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);
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logic [15:0] RandomNumber1;
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c_rand RNG1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.out( RandomNumber1[15:0] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100.2 start = 1'b1;
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#5 start = 1'b0;
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end
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// Module under test ==========================================================
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logic [1:0][7:0] in;
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assign in = RandomNumber1[15:0];
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logic [7:0][1:0] out;
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reverse_dimensions #(
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.D1_WIDTH( 2 ),
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.D2_WIDTH( 8 )
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) RD1 (
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.in( in ),
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.out( out )
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);
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endmodule

‎reverse_dimensions_tb/wave.do

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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -radix binary -childformat {{{/reverse_dimensions_tb/RD1/in[1]} -radix binary} {{/reverse_dimensions_tb/RD1/in[0]} -radix binary}} -expand -subitemconfig {{/reverse_dimensions_tb/RD1/in[1]} {-radix binary} {/reverse_dimensions_tb/RD1/in[0]} {-radix binary}} /reverse_dimensions_tb/RD1/in
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add wave -noupdate -radix binary -childformat {{{/reverse_dimensions_tb/RD1/out[7]} -radix binary} {{/reverse_dimensions_tb/RD1/out[6]} -radix binary} {{/reverse_dimensions_tb/RD1/out[5]} -radix binary} {{/reverse_dimensions_tb/RD1/out[4]} -radix binary -childformat {{{[1]} -radix hexadecimal} {{[0]} -radix hexadecimal}}} {{/reverse_dimensions_tb/RD1/out[3]} -radix binary} {{/reverse_dimensions_tb/RD1/out[2]} -radix binary} {{/reverse_dimensions_tb/RD1/out[1]} -radix binary} {{/reverse_dimensions_tb/RD1/out[0]} -radix binary}} -expand -subitemconfig {{/reverse_dimensions_tb/RD1/out[7]} {-radix binary} {/reverse_dimensions_tb/RD1/out[6]} {-radix binary} {/reverse_dimensions_tb/RD1/out[5]} {-radix binary} {/reverse_dimensions_tb/RD1/out[4]} {-radix binary -childformat {{{[1]} -radix hexadecimal} {{[0]} -radix hexadecimal}}} {/reverse_dimensions_tb/RD1/out[4][1]} {-radix hexadecimal} {/reverse_dimensions_tb/RD1/out[4][0]} {-radix hexadecimal} {/reverse_dimensions_tb/RD1/out[3]} {-radix binary} {/reverse_dimensions_tb/RD1/out[2]} {-radix binary} {/reverse_dimensions_tb/RD1/out[1]} {-radix binary} {/reverse_dimensions_tb/RD1/out[0]} {-radix binary}} /reverse_dimensions_tb/RD1/out
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {21806 ps} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue right
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {4609 ps} {81173 ps}

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