Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
18 commits
Select commit Hold shift + click to select a range
96daba1
modified conf.py file
MustafaAbdaal Oct 28, 2024
e2358e7
Modified main index.rst & created User Guide index.rst
MustafaAbdaal Oct 31, 2024
653b914
Updated each section's .rst file with subsections
MustafaAbdaal Oct 31, 2024
8dfe5d8
Merge branch 'main' into user-guide-ToC
MustafaAbdaal Nov 1, 2024
1a3527b
Merge branch 'main' into user-guide-ToC
MustafaAbdaal Nov 5, 2024
d04229a
adding sections folders for images and code snippets
MustafaAbdaal Nov 5, 2024
e1834fd
Adding screenshots to main figure folder
MustafaAbdaal Nov 12, 2024
9503ab4
edited SoC Input section to include peripherals, connectivity, memory…
MustafaAbdaal Nov 15, 2024
bcefdf5
Completed initial draft content for setup section. figures will be fo…
MustafaAbdaal Nov 15, 2024
c307a6e
Merge branch 'main' of github.com:os-fpga/rapid_power_estimator into …
MustafaAbdaal Nov 15, 2024
7eb0f23
Finished writing initial content for SoC input section on SoC_index.rst
MustafaAbdaal Nov 19, 2024
f35309c
Added screenshots and general instructions to fill out FPGA input, mo…
MustafaAbdaal Nov 20, 2024
735b7b0
Added initial instructions for BRAM, DSP & IO subsections of FPGA input
MustafaAbdaal Nov 20, 2024
5929f65
Modified FPGA input content to explicity mention fields and their def…
MustafaAbdaal Nov 27, 2024
2dc4679
Fixed a few labels that were identified during walkthrough session
MustafaAbdaal Nov 28, 2024
d012b2a
Merge branch 'main' into user-guide-ToC
MustafaAbdaal Nov 28, 2024
a0489b6
Replaced some screenshots with most recent RPE version's screenshots …
MustafaAbdaal Dec 2, 2024
6510d79
Merge branch 'main' into user-guide-ToC
MustafaAbdaal Dec 2, 2024
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
30 changes: 0 additions & 30 deletions docs/source/user_guide/FPGA.rst

This file was deleted.

4 changes: 2 additions & 2 deletions docs/source/user_guide/FPGA_index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ The BRAM section is located directly below the clocking section.

Selecting the BRAM section displays an empty table, click the "Add" button above the table to fill out the BRAM info.

.. image:: figures/FPGA-figures-BRAM-input_BRAM_info.JPG
.. image:: figures/FPGA-figures-BRAM-input_BRAM_info_v2.JPG

.. image:: figures/FPGA-figures-BRAM-input_BRAM_ports_info.JPG

Expand All @@ -84,7 +84,7 @@ The DSP section is located directly below the FLE section.

Selecting the DSP section displays an empty table, click the "Add" button above the table to fill out the DSP info.

.. image:: figures/FPGA-figures-DSP-input_DSP_info.JPG
.. image:: figures/FPGA-figures-DSP-input_DSP_info_v2.JPG

1. Provide a name to label the DSP function within the hierarchy (optional)
2. Enter the no. of DSP multipliers
Expand Down
17 changes: 0 additions & 17 deletions docs/source/user_guide/SoC.rst

This file was deleted.

10 changes: 5 additions & 5 deletions docs/source/user_guide/SoC_index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ Then click on each enabled peripheral's action column button to configure the pe

For each peripheral, select it's usage as well as performance.

*Note:* For PWM, selecting an IO is also required to drive the PWM signal.
*Note: For PWM, selecting an IO is also required to drive the PWM signal.*

BCPU - Boot Central Processing Unit
#######################################
Expand All @@ -29,12 +29,12 @@ The BCPU section is found at the top of the SoC input section, to the left of th

Selecting the BCPU section will display the name of the CPU "N22 RISC-V", followed by it's configuration fields.

.. image:: figures/SoC-figures-BCPU-BPCU_selected.JPG
.. image:: figures/SoC-figures-BCPU-BCPU_selected_v2.JPG

Enable/Disable encryption using the checkbox.

Select Boot Mode, SPI is selected by default.
*note:* SPI is currently the only available mode.
*note: SPI is currently the only available mode.*

Select Clock, BOOT CLK is selected by default.

Expand Down Expand Up @@ -72,7 +72,7 @@ Selecting the memory section will display a table below with the available memor

For each memory, select it's usage, then Memory Type, followed by required Data Rate & channel width.

*Note:* All devices will have OCM - on chip memory, DDR memory is only available on specific devices.
*Note: All devices will have OCM - on chip memory, DDR memory is only available on specific devices.*

.. image:: figures/memory-figures-input_DDR_memory_info.JPG

Expand All @@ -83,7 +83,7 @@ The ACPU section is found on the top left of the SoC input display.

.. image:: figures/SoC-figures-ACPU-ACPU_selected.JPG

Selecting the ACPU section will display the name of the CPU, followed by it's operating frequency & Load selection. *Note:* Application CPU is not available on all devices.
Selecting the ACPU section will display the name of the CPU, followed by it's operating frequency & Load selection. *Note: Application CPU is not available on all devices.*

Toggle the ACPU Power toggle switch on left hand side to enable ACPU, then select the load required from the Load dropdown.

Expand Down
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
Loading
Sorry, something went wrong. Reload?
Sorry, we cannot display this file.
Sorry, this file is invalid so it cannot be displayed.
6 changes: 0 additions & 6 deletions docs/source/user_guide/introduction.rst

This file was deleted.

14 changes: 0 additions & 14 deletions docs/source/user_guide/results.rst

This file was deleted.

34 changes: 33 additions & 1 deletion docs/source/user_guide/results_index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,44 @@ Analyzing Results
====================

This section will document the results on Rapid Power Estimator.
The Rapid Power Estimator provides a comprehensive power data display on the right hand side of the user interface.

.. image:: figures/results-figures-Display.JPG


FPGA Complex & Core Power
#########################

The FPGA Power Data is displayed below the save icon and top level module input field.

.. image:: figures/results-figures-FPGA_Complex_and_Core_Power.JPG

The Display shows each FPGA input section label with 2 columns for power in watts & the percentage of power used by each respective part of the FPGA design.

The last 2 rows show FPGA Dynamic Power & FPGA Static Power. The power data in these rows is the sum of the respective static and dynamic power values from each of the FPGA input sections.

At the bottom of the display, an overall percentage is given along with a percentage bar, this shows the percentage of power being used by the FPGA within the overall FPGA SoC.

Processing Complex (SoC) Power
##############################

The SoC Power Data is displayed on the far right of the screen, to the right of FPGA Power Data display.

.. image:: figures/results-figures-SoC_Processing_Complex_Power.JPG

The display shows each SoC input section label with 2 columns for power in watts & the percentage of power used by each respective part of the SoC's Processing Complex.

The last 2 rows shows overall Dynamic & Static Power. The Power data in these rows is the sum of the respective static and dynamic power values from each of the SoC input sections.

At the bottom of the display, an overall percentage is given along with a percentage bar, this shows the percentage of power being used by the Processing Complex within the overall FPGA SoC.


Overall Typical & Worst Case Power
##################################
##################################

The Overall power budget numbers are displayed at the top right hand side of the screen, above the Processing Complex Power Display.

.. image:: figures/results-figures-Overal_Power_Typical_and_Worst.JPG

The displays show power in watts on a typical operating temperature of 25 degrees celcius as well as a power in watts on a worst case operating temperature of 81 degrees celcius.

14 changes: 0 additions & 14 deletions docs/source/user_guide/setup.rst

This file was deleted.

2 changes: 1 addition & 1 deletion docs/source/user_guide/setup_index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ Launching RPE

To launch the Rapid Power Estimator, simply navigate to your start menu and search for "Rapid Power Estimator". Once the application is found, click on the application icon to launch the tool.

.. image:: figures/setup-figures-launching_RPE_from_windows_start_menu.JPG
.. image:: figures/setup-figures-launching_RPE_from_windows_start_menu_v2.JPG
:alt: RPE icon on windows start menu

The Rapid Power Estimator will display the following screen upon launch.
Expand Down
Loading