[Intel-SIG] backport Intel microcode staging feature #94
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commit 7cdda85ed90c1abaccaf5f05ec217acbc102c164 upstream.
As microcode patch sizes continue to grow, late-loading latency spikes can
lead to timeouts and disruptions in running workloads. This trend of
increasing patch sizes is expected to continue, so a foundational solution is
needed to address the issue.
To mitigate the problem, introduce a microcode staging feature. This option
processes most of the microcode update (excluding activation) on
a non-critical path, allowing CPUs to remain operational during the majority
of the update. By offloading work from the critical path, staging can
significantly reduce latency spikes.
Integrate staging as a preparatory step in late-loading. Introduce a new
callback for staging, which is invoked at the beginning of
load_late_stop_cpus(), before CPUs enter the rendezvous phase.
Staging follows an opportunistic model:
* If successful, it reduces CPU rendezvous time
* Even though it fails, the process falls back to the legacy path to
finish the loading process but with potentially higher latency.
Extend struct microcode_ops to incorporate staging properties, which will be
implemented in the vendor code separately.
Intel-SIG: commit 7cdda85ed90c x86/microcode: Introduce staging step to reduce late-loading time.
Backport to support Intel microcode staging feature
Signed-off-by: Chang S. Bae <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Chao Gao <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
Tested-by: Anselm Busse <[email protected]>
Link: https://lore.kernel.org/[email protected]
[ Aubrey Li: amend commit log ]
Signed-off-by: Aubrey Li <[email protected]>
commit 740144bc6bde9d44e3a6c224cee6fe971a08fbca upstream.
When microcode staging is initiated, operations are carried out through
an MMIO interface. Each package has a unique interface specified by the
IA32_MCU_STAGING_MBOX_ADDR MSR, which maps to a set of 32-bit registers.
Prepare staging with the following steps:
1. Ensure the microcode image is 32-bit aligned to match the MMIO
register size.
2. Identify each MMIO interface based on its per-package scope.
3. Invoke the staging function for each identified interface, which
will be implemented separately.
[ bp: Improve error logging. ]
Intel-SIG: commit 740144bc6bde x86/microcode/intel: Establish staging control logic.
Backport to support Intel microcode staging feature
Suggested-by: Thomas Gleixner <[email protected]>
Signed-off-by: Chang S. Bae <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
Tested-by: Anselm Busse <[email protected]>
Link: https://lore.kernel.org/all/871pznq229.ffs@tglx
[ Aubrey Li: amend commit log ]
Signed-off-by: Aubrey Li <[email protected]>
commit 079b90d4ba8dfa9603ecf400556894224021452d upstream. Define a staging_state struct to simplify function prototypes by consolidating relevant data, instead of passing multiple local variables. Intel-SIG: commit 079b90d4ba8d x86/microcode/intel: Define staging state struct. Backport to support Intel microcode staging feature Signed-off-by: Chang S. Bae <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Tony Luck <[email protected]> Tested-by: Anselm Busse <[email protected]> Link: https://lore.kernel.org/[email protected] [ Aubrey Li: amend commit log ] Signed-off-by: Aubrey Li <[email protected]>
commit afc3b5095461de8ca463a18f29a4ef6bdb92c2be upstream.
Previously, per-package staging invocations and their associated state
data were established. The next step is to implement the actual staging
handler according to the specified protocol. Below are key aspects to
note:
(a) Each staging process must begin by resetting the staging hardware.
(b) The staging hardware processes up to a page-sized chunk of the
microcode image per iteration, requiring software to submit data
incrementally.
(c) Once a data chunk is processed, the hardware responds with an
offset in the image for the next chunk.
(d) The offset may indicate completion or request retransmission of an
already transferred chunk. As long as the total transferred data
remains within the predefined limit (twice the image size),
retransmissions should be acceptable.
Incorporate them in the handler, while data transmission and mailbox
format handling are implemented separately.
[ bp: Sort the headers in a reversed name-length order. ]
Intel-SIG: commit afc3b5095461 x86/microcode/intel: Implement staging handler.
Backport to support Intel microcode staging feature
Signed-off-by: Chang S. Bae <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Tony Luck <[email protected]>
Tested-by: Anselm Busse <[email protected]>
Link: https://lore.kernel.org/[email protected]
[ Aubrey Li: amend commit log ]
Signed-off-by: Aubrey Li <[email protected]>
commit 4ab410287bfd33e64073d8003b439da10356769d upstream. The functions for sending microcode data and retrieving the next offset were previously placeholders, as they need to handle a specific mailbox format. While the kernel supports similar mailboxes, none of them are compatible with this one. Attempts to share code led to unnecessary complexity, so add a dedicated implementation instead. [ bp: Sort the include properly. ] Intel-SIG: commit 4ab410287bfd x86/microcode/intel: Support mailbox transfer. Backport to support Intel microcode staging feature Signed-off-by: Chang S. Bae <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Tony Luck <[email protected]> Tested-by: Anselm Busse <[email protected]> Link: https://lore.kernel.org/[email protected] [ Aubrey Li: amend commit log ] Signed-off-by: Aubrey Li <[email protected]>
commit bffeb2fd0b9c99d8af348da88335bff408c63882 upstream. With staging support implemented, enable it when the CPU reports the feature. [ bp: Sort in the MSR properly. ] Intel-SIG: commit bffeb2fd0b9c x86/microcode/intel: Enable staging when available. Backport to support Intel microcode staging feature Signed-off-by: Chang S. Bae <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Chao Gao <[email protected]> Reviewed-by: Tony Luck <[email protected]> Tested-by: Anselm Busse <[email protected]> Link: https://lore.kernel.org/[email protected] [ Aubrey Li: amend commit log ] Signed-off-by: Aubrey Li <[email protected]>
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backport Intel microcode staging feature, there are 7 patches totally.
Patch 0001-x86-cpu-topology-Make-primary-thread-mask-available-.patch heavily depends on CPU toplogy patch series and will be handled after CPU topology patch series merged.
Passed test:
# echo 1 > /sys/devices/system/cpu/microcode/reload# dmesg | grep microcode[ 12.090791] microcode: Enabled staging feature.[ 12.098249] microcode: Current revision: 0x800002b0[ 12.111873] microcode: Microcode Update Driver: v2.2.[ 93.742725] microcode: Staging of patch revision 0x800002f0 succeeded.[ 94.061781] microcode: Updated to revision 0x800002f0, date = 2025-06-04[ 97.896386] microcode: load: updated on 144 primary CPUs with 0 siblings[ 97.904576] microcode: revision: 0x800002b0 -> 0x800002f0