grlib-gpl-1.3.7-b4144

bin/gpl.sed

@@ -1,7 +1,7 @@
 s/--GAISLER_LICENSE/------------------------------------------------------------------------------\
 --  This file is a part of the GRLIB VHDL IP LIBRARY\
 --  Copyright (C) 2003 - 2008, Gaisler Research\
---  Copyright (C) 2008 - 2013, Aeroflex Gaisler\
+--  Copyright (C) 2008 - 2014, Aeroflex Gaisler\
 --\
 --  This program is free software\; you can redistribute it and\/or modify\
 --  it under the terms of the GNU General Public License as published by\

bin/gr.sed

@@ -1,6 +1,6 @@
 s/--GAISLER_LICENSE/------------------------------------------------------------------------------\
 --  This file is a part of the GRLIB VHDL IP LIBRARY\
---  Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.\
+--  Copyright (C) 2014, Aeroflex Gaisler AB - all rights reserved.\
 --\
 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN \
 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED \

boards/gr-cpci-xc4v/leon3mp.ucf

@@ -382,12 +382,12 @@ NET "pci_arb_gnt(6)" LOC = "AT25" | IOSTANDARD=PCI33_3; #pci_gntn(6)
 NET "pci_arb_gnt(7)" LOC = "AU21" | IOSTANDARD=PCI33_3; #pci_gntn(7)
 
 NET "pci_arb_req(0)" LOC = "AV22" | IOSTANDARD=PCI33_3; #pci_reqn(0)
-NET "pci_arb_req(1)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(1)
+NET "pci_arb_req(1)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(1)
 NET "pci_arb_req(2)" LOC = "AW26" | IOSTANDARD=PCI33_3; #pci_reqn(2)
 NET "pci_arb_req(3)" LOC = "AV24" | IOSTANDARD=PCI33_3; #pci_reqn(3)
 NET "pci_arb_req(4)" LOC = "AV25" | IOSTANDARD=PCI33_3; #pci_reqn(4)
-NET "pci_arb_req(5)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(5)
-NET "pci_arb_req(6)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(6)
+NET "pci_arb_req(5)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(5)
+NET "pci_arb_req(6)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(6)
 NET "pci_arb_req(7)" LOC = "AW22" | IOSTANDARD=PCI33_3; #pci_reqn(7)
 
 NET "pci_idsel"   LOC = "AV9"  | IOSTANDARD=PCI33_3 | BYPASS;

boards/gr-cpci-xc4vlx200/leon3mp.ucf

@@ -217,14 +217,14 @@ NET "sd(61)" LOC = "C29" | IOSTANDARD=LVTTL;
 NET "sd(62)" LOC = "J22" | IOSTANDARD=LVTTL;
 NET "sd(63)" LOC = "G30" | IOSTANDARD=LVTTL;
 
-NET "sdcke(0)" LOC = "A18"  | IOSTANDARD=LVTTL;
-NET "sdcke(1)" LOC = "B18"  | IOSTANDARD=LVTTL;
+NET "sdcke(0)" LOC = "B18"  | IOSTANDARD=LVTTL;
+NET "sdcke(1)" LOC = "A18"  | IOSTANDARD=LVTTL;
 NET "sdcke(2)" LOC = "D22"  | IOSTANDARD=LVTTL;
-NET "sdcke(3)" LOC = "F29"  | IOSTANDARD=LVTTL;
+NET "sdcke(3)" LOC = "E26"  | IOSTANDARD=LVTTL;
 
 NET "sdcsn(0)" LOC = "D21"  | IOSTANDARD=LVTTL;
 NET "sdcsn(1)" LOC = "A24"  | IOSTANDARD=LVTTL;
-NET "sdcsn(2)" LOC = "E21"  | IOSTANDARD=LVTTL;
+NET "sdcsn(2)" LOC = "D20"  | IOSTANDARD=LVTTL;
 NET "sdcsn(3)" LOC = "E22"  | IOSTANDARD=LVTTL;
 
 NET "sddqm(0)" LOC = "E11" | IOSTANDARD=LVTTL;
@@ -240,9 +240,9 @@ NET "sdcasn" LOC = "G22" | IOSTANDARD=LVTTL;
 NET "sdrasn" LOC = "B25" | IOSTANDARD=LVTTL;
 NET "sdwen"  LOC = "A25" | IOSTANDARD=LVTTL;
 
-NET "sdscl"    LOC = "B36" | IOSTANDARD=LVTTL;
-NET "sdsda(0)" LOC = "B37" | IOSTANDARD=LVTTL;
-NET "sdsda(1)" LOC = "G33" | IOSTANDARD=LVTTL;
+NET "sdscl"    LOC = "C39" | IOSTANDARD=LVTTL;
+NET "sdsda(0)" LOC = "C38" | IOSTANDARD=LVTTL;
+NET "sdsda(1)" LOC = "C37" | IOSTANDARD=LVTTL;
 
 
 NET "dsuact" LOC = "D34" | IOSTANDARD=LVTTL;
@@ -318,10 +318,10 @@ NET "pci_ad(40)" LOC = "AR38" | IOSTANDARD=PCI33_3;
 NET "pci_ad(41)" LOC = "AP36" | IOSTANDARD=PCI33_3;
 NET "pci_ad(42)" LOC = "AR36" | IOSTANDARD=PCI33_3;
 NET "pci_ad(43)" LOC = "AT36" | IOSTANDARD=PCI33_3;
-NET "pci_ad(44)" LOC = "AN33" | IOSTANDARD=PCI33_3;
-NET "pci_ad(45)" LOC = "AR34" | IOSTANDARD=PCI33_3;
+NET "pci_ad(44)" LOC = "AP34" | IOSTANDARD=PCI33_3;
+NET "pci_ad(45)" LOC = "AT35" | IOSTANDARD=PCI33_3;
 NET "pci_ad(46)" LOC = "AU36" | IOSTANDARD=PCI33_3;
-NET "pci_ad(47)" LOC = "AT35" | IOSTANDARD=PCI33_3;
+NET "pci_ad(47)" LOC = "AR34" | IOSTANDARD=PCI33_3;
 NET "pci_ad(48)" LOC = "AT39" | IOSTANDARD=PCI33_3;
 NET "pci_ad(49)" LOC = "AT38" | IOSTANDARD=PCI33_3;
 NET "pci_ad(50)" LOC = "AU38" | IOSTANDARD=PCI33_3;
@@ -332,12 +332,12 @@ NET "pci_ad(54)" LOC = "AU33" | IOSTANDARD=PCI33_3;
 NET "pci_ad(55)" LOC = "AU35" | IOSTANDARD=PCI33_3;
 NET "pci_ad(56)" LOC = "AV37" | IOSTANDARD=PCI33_3;
 NET "pci_ad(57)" LOC = "AW37" | IOSTANDARD=PCI33_3;
-NET "pci_ad(58)" LOC = "AM35" | IOSTANDARD=PCI33_3;
+NET "pci_ad(58)" LOC = "AN34" | IOSTANDARD=PCI33_3;
 NET "pci_ad(59)" LOC = "AW35" | IOSTANDARD=PCI33_3;
 NET "pci_ad(60)" LOC = "AW36" | IOSTANDARD=PCI33_3;
 NET "pci_ad(61)" LOC = "AV35" | IOSTANDARD=PCI33_3;
 NET "pci_ad(62)" LOC = "AT33" | IOSTANDARD=PCI33_3;
-NET "pci_ad(63)" LOC = "AP34" | IOSTANDARD=PCI33_3;
+NET "pci_ad(63)" LOC = "AR33" | IOSTANDARD=PCI33_3;
 NET "pci_cbe(0)" LOC = "AT13" | IOSTANDARD=PCI33_3;
 NET "pci_cbe(1)" LOC = "AU12" | IOSTANDARD=PCI33_3;
 NET "pci_cbe(2)" LOC = "AR13" | IOSTANDARD=PCI33_3;
@@ -367,12 +367,12 @@ NET "pci_arb_gnt(6)" LOC = "AT25" | IOSTANDARD=PCI33_3; #pci_gntn(6)
 NET "pci_arb_gnt(7)" LOC = "AU21" | IOSTANDARD=PCI33_3; #pci_gntn(7)
 
 NET "pci_arb_req(0)" LOC = "AV22" | IOSTANDARD=PCI33_3; #pci_reqn(0)
-NET "pci_arb_req(1)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(1)
+NET "pci_arb_req(1)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(1)
 NET "pci_arb_req(2)" LOC = "AW26" | IOSTANDARD=PCI33_3; #pci_reqn(2)
 NET "pci_arb_req(3)" LOC = "AV24" | IOSTANDARD=PCI33_3; #pci_reqn(3)
 NET "pci_arb_req(4)" LOC = "AV25" | IOSTANDARD=PCI33_3; #pci_reqn(4)
-NET "pci_arb_req(5)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(5)
-NET "pci_arb_req(6)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(6)
+NET "pci_arb_req(5)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(5)
+NET "pci_arb_req(6)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(6)
 NET "pci_arb_req(7)" LOC = "AW22" | IOSTANDARD=PCI33_3; #pci_reqn(7)
 
 NET "pci_idsel"   LOC = "AV9"  | IOSTANDARD=LVTTL;

boards/gr-xc6s/Makefile.inc

@@ -16,4 +16,4 @@ PLANAHEAD_SYNTH_FLOW="XST 14"
 PLANAHEAD_SYNTH_STRATEGY="TimingWithIOBPacking"
 
 # Set PlanAhead Implementation strategy
-PLANAHEAD_IMPL_STRATEGY="MapLogicOptParHighExtra"
+PLANAHEAD_IMPL_STRATEGY="MapGlobalOptLogicOptRetimingDupParHigh"

boards/terasic-de4/ddr2ctrl.vhd

@@ -2,7 +2,7 @@
 -- GENERATION: XML
 -- ddr2ctrl.vhd
 
--- Generated using ACDS version 13.1 162 at 2013.12.06.15:39:20
+-- Generated using ACDS version 13.1 162 at 2014.03.03.20:01:23
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -40,7 +40,7 @@ entity ddr2ctrl is
 		avl_be             : in    std_logic_vector(31 downto 0)  := (others => '0'); --                 .byteenable
 		avl_read_req       : in    std_logic                      := '0';             --                 .read
 		avl_write_req      : in    std_logic                      := '0';             --                 .write
-		avl_size           : in    std_logic_vector(2 downto 0)   := (others => '0'); --                 .burstcount
+		avl_size           : in    std_logic_vector(3 downto 0)   := (others => '0'); --                 .burstcount
 		local_init_done    : out   std_logic;                                         --           status.local_init_done
 		local_cal_success  : out   std_logic;                                         --                 .local_cal_success
 		local_cal_fail     : out   std_logic;                                         --                 .local_cal_fail
@@ -82,7 +82,7 @@ architecture rtl of ddr2ctrl is
 			avl_be             : in    std_logic_vector(31 downto 0)  := (others => 'X'); -- byteenable
 			avl_read_req       : in    std_logic                      := 'X';             -- read
 			avl_write_req      : in    std_logic                      := 'X';             -- write
-			avl_size           : in    std_logic_vector(2 downto 0)   := (others => 'X'); -- burstcount
+			avl_size           : in    std_logic_vector(3 downto 0)   := (others => 'X'); -- burstcount
 			local_init_done    : out   std_logic;                                         -- local_init_done
 			local_cal_success  : out   std_logic;                                         -- local_cal_success
 			local_cal_fail     : out   std_logic;                                         -- local_cal_fail
@@ -140,7 +140,7 @@ end architecture rtl; -- of ddr2ctrl
 --	************************************************************
 --	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --	************************************************************
---	Copyright (C) 1991-2013 Altera Corporation
+--	Copyright (C) 1991-2014 Altera Corporation
 --	Any megafunction design, and related net list (encrypted or decrypted),
 --	support information, device programming or simulation file, and any other
 --	associated documentation or information provided by Altera or a partner
@@ -211,9 +211,9 @@ end architecture rtl; -- of ddr2ctrl
 -- Retrieval info: 	<generic name="MEM_INIT_FILE" value="" />
 -- Retrieval info: 	<generic name="DAT_DATA_WIDTH" value="32" />
 -- Retrieval info: 	<generic name="TIMING_TIS" value="375" />
--- Retrieval info: 	<generic name="TIMING_TIH" value="375" />
+-- Retrieval info: 	<generic name="TIMING_TIH" value="500" />
 -- Retrieval info: 	<generic name="TIMING_TDS" value="250" />
--- Retrieval info: 	<generic name="TIMING_TDH" value="250" />
+-- Retrieval info: 	<generic name="TIMING_TDH" value="300" />
 -- Retrieval info: 	<generic name="TIMING_TDQSQ" value="200" />
 -- Retrieval info: 	<generic name="TIMING_TQHS" value="300" />
 -- Retrieval info: 	<generic name="TIMING_TDQSCK" value="350" />
@@ -252,7 +252,7 @@ end architecture rtl; -- of ddr2ctrl
 -- Retrieval info: 	<generic name="CUT_NEW_FAMILY_TIMING" value="true" />
 -- Retrieval info: 	<generic name="POWER_OF_TWO_BUS" value="false" />
 -- Retrieval info: 	<generic name="SOPC_COMPAT_RESET" value="false" />
--- Retrieval info: 	<generic name="AVL_MAX_SIZE" value="4" />
+-- Retrieval info: 	<generic name="AVL_MAX_SIZE" value="8" />
 -- Retrieval info: 	<generic name="BYTE_ENABLE" value="true" />
 -- Retrieval info: 	<generic name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
 -- Retrieval info: 	<generic name="CTL_DEEP_POWERDN_EN" value="false" />
@@ -265,7 +265,7 @@ end architecture rtl; -- of ddr2ctrl
 -- Retrieval info: 	<generic name="ADDR_ORDER" value="0" />
 -- Retrieval info: 	<generic name="CTL_LOOK_AHEAD_DEPTH" value="4" />
 -- Retrieval info: 	<generic name="CONTROLLER_LATENCY" value="5" />
--- Retrieval info: 	<generic name="CFG_REORDER_DATA" value="true" />
+-- Retrieval info: 	<generic name="CFG_REORDER_DATA" value="false" />
 -- Retrieval info: 	<generic name="STARVE_LIMIT" value="10" />
 -- Retrieval info: 	<generic name="CTL_CSR_ENABLED" value="false" />
 -- Retrieval info: 	<generic name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />

boards/xilinx-ac701-xc7a200t/Makefile.inc

@@ -0,0 +1,29 @@
+# FPGA and Dev Board used in Design
+TECHNOLOGY=kintex7
+PART=xc7a200t
+PACKAGE=fbg676
+PROTOBOARD=xilinx.com:artix7:ac701:1.0
+SPEED=2
+PROMGENPAR=-x xcf08p -u 0 $(TOP).bit -p mcs -w -o $(BOARD)
+
+# Set Vivado Synthesis Flow and Strategy used for build
+# Choose 'XST 14' or 'Vivado Synthesis 2012'
+#VIVADO_SYNTH_FLOW="Vivado Synthesis 2012"
+
+# For 'Vivado Synthesis 2012' flow set:
+#    1. 'Vivado Synthesis Defaults'
+# For 'XST 14'flow set:
+#    1. 'TimingWithIOBPacking'
+#    2. 'TimingWithoutIOBPacking'
+#    3. 'AreaReduction'
+#    4. 'PowerOptimization'
+#    5. 'XST Defaults'
+#VIVADO_SYNTH_STRATEGY="Vivado Synthesis Defaults"
+
+# Set Vivado Implementation strategy
+#   1. 'HighEffort'
+#   2. 'HighEffortPhySynth'
+#   3. 'Vivado Implemnation Defaults'
+#   4. 'LowEffort'
+#   5. 'QuickEffort'
+#VIVADO_IMPL_STRATEGY="HighEffortPhySynth"

boards/xilinx-ac701-xc7a200t/default.ut

@@ -0,0 +1,26 @@
+-g DebugBitstream:No
+-g Binary:no
+-b
+-g CRC:Enable
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g StartUpClk:CCLK
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g Persist:No
+-g ReadBack
+-g DonePipe:No
+-g DriveDone:Yes

boards/xilinx-ac701-xc7a200t/fpga-usb.cmd

@@ -0,0 +1,25 @@
+setPreference -pref UserLevel:NOVICE
+setPreference -pref MessageLevel:DETAILED
+setPreference -pref ConcurrentMode:FALSE
+setPreference -pref UseHighz:FALSE
+setPreference -pref ConfigOnFailure:STOP
+setPreference -pref StartupCLock:AUTO_CORRECTION
+setPreference -pref AutoSignature:FALSE
+setPreference -pref KeepSVF:FALSE
+setPreference -pref svfUseTime:FALSE
+setPreference -pref UserLevel:NOVICE
+setPreference -pref MessageLevel:DETAILED
+setPreference -pref ConcurrentMode:FALSE
+setPreference -pref UseHighz:FALSE
+setPreference -pref ConfigOnFailure:STOP
+setPreference -pref StartupCLock:AUTO_CORRECTION
+setPreference -pref AutoSignature:FALSE
+setPreference -pref KeepSVF:FALSE
+setPreference -pref svfUseTime:FALSE
+setMode -bs
+setCable -port usb21
+Identify
+setAttribute -position 1 -attr configFileName -value "xilinx-ac701-xc7a200t.bit"
+Program -p 1 -v 
+setMode -bs
+quit

boards/xilinx-ac701-xc7a200t/fpga.cmd

@@ -0,0 +1,25 @@
+setPreference -pref UserLevel:NOVICE
+setPreference -pref MessageLevel:DETAILED
+setPreference -pref ConcurrentMode:FALSE
+setPreference -pref UseHighz:FALSE
+setPreference -pref ConfigOnFailure:STOP
+setPreference -pref StartupCLock:AUTO_CORRECTION
+setPreference -pref AutoSignature:FALSE
+setPreference -pref KeepSVF:FALSE
+setPreference -pref svfUseTime:FALSE
+setPreference -pref UserLevel:NOVICE
+setPreference -pref MessageLevel:DETAILED
+setPreference -pref ConcurrentMode:FALSE
+setPreference -pref UseHighz:FALSE
+setPreference -pref ConfigOnFailure:STOP
+setPreference -pref StartupCLock:AUTO_CORRECTION
+setPreference -pref AutoSignature:FALSE
+setPreference -pref KeepSVF:FALSE
+setPreference -pref svfUseTime:FALSE
+setMode -bs
+setCable -port auto
+Identify
+setAttribute -position 1 -attr configFileName -value "xilinx-ac701-xc7a200t.bit"
+Program -p 1 -v 
+setMode -bs
+quit