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[msm7x30]: Enable LCDC display for msm7x30 devices
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-- Add code to configure Toshiba LCDC panels
-- Add support for MDP4 LCDC mode.

Change-Id: I3846a146b98d19038779d8088cf64becff087a89
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Shashank Mittal authored and Linux Build Service Account committed Sep 12, 2010
1 parent 3c1ec4c commit 3704083
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Showing 12 changed files with 559 additions and 107 deletions.
3 changes: 3 additions & 0 deletions dev/fbcon/fbcon.c
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Original file line number Diff line number Diff line change
Expand Up @@ -190,6 +190,9 @@ void fbcon_setup(struct fbcon_config *_config)
cur_pos.y = 0;
max_pos.x = config->width / (FONT_WIDTH+1);
max_pos.y = (config->height - 1) / FONT_HEIGHT;
#if !DISPLAY_SPLASH_SCREEN
fbcon_clear();
#endif
}

struct fbcon_config* fbcon_display(void)
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10 changes: 10 additions & 0 deletions dev/keys/gpio_keypad.c
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Original file line number Diff line number Diff line change
Expand Up @@ -542,3 +542,13 @@ void ssbi_keypad_init(struct qwerty_keypad_info *qwerty_kp)
event_wait(&qwerty_keypad->full_scan);
}

void pmic_write(unsigned address, unsigned data)
{
write_func wr_function = &i2c_ssbi_write_bytes;
if(wr_function == NULL)
return;
if ((*wr_function)(&data, 1, address))
dprintf (CRITICAL, "Error in initializing register\n");

}

39 changes: 30 additions & 9 deletions platform/msm7x30/gpio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,8 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
Expand Down Expand Up @@ -132,17 +134,16 @@ static gpioregs GPIO_REGS[] = {

static gpioregs *find_gpio(unsigned n, unsigned *bit)
{
if(n > 164) return 0;
if(n > 152) {
*bit = 1 << (n - 153);
if(n > 150) {
*bit = 1 << (n - 151);
return GPIO_REGS + 7;
}
if(n > 121) {
*bit = 1 << (n - 122);
if(n > 133) {
*bit = 1 << (n - 134);
return GPIO_REGS + 6;
}
if(n > 103) {
*bit = 1 << (n - 104);
if(n > 106) {
*bit = 1 << (n - 107);
return GPIO_REGS + 5;
}
if(n > 94) {
Expand All @@ -153,8 +154,8 @@ static gpioregs *find_gpio(unsigned n, unsigned *bit)
*bit = 1 << (n - 68);
return GPIO_REGS + 3;
}
if(n > 42) {
*bit = 1 << (n - 43);
if(n > 43) {
*bit = 1 << (n - 44);
return GPIO_REGS + 2;
}
if(n > 15) {
Expand Down Expand Up @@ -218,3 +219,23 @@ void platform_config_interleaved_mode_gpios(void)
writel (GPIO_ALT_FUNC_PAGE_REG, 0x73);
writel (GPIO_ALT_FUNC_CFG_REG, 0x08);
}

/* Enables all gpios passed in table*/
int platform_gpios_enable(const struct msm_gpio *table, int size)
{
int rc;
int i;
const struct msm_gpio *g;
for (i = 0; i < size; i++) {
g = table + i;
/* Enable gpio */
rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
if (rc) {
goto err;
}
}
return 0;
err:
return rc;
}

174 changes: 115 additions & 59 deletions platform/msm7x30/gpio_hw.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,8 @@
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
Expand Down Expand Up @@ -29,95 +31,149 @@
#ifndef __PLATFORM_MSM7X30_GPIO_HW_H
#define __PLATFORM_MSM7X30_GPIO_HW_H

#define MSM_GPIO1_BASE 0xA9000000
#define MSM_GPIO2_BASE 0xA9100000
#define MSM_GPIO1_BASE 0xAC001000
#define MSM_GPIO2_BASE 0xAC101000

#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
#define GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))

/* output value */
#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 43-16 */
#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-44 */
#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 103-95 */
#define GPIO_OUT_5 GPIO1_REG(0x10) /* gpio 121-104 */
#define GPIO_OUT_6 GPIO1_REG(0x14) /* gpio 152-122 */
#define GPIO_OUT_7 GPIO1_REG(0x18) /* gpio 164-153 */
#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 133-107 */
#define GPIO_OUT_6 GPIO1_REG(0xC4) /* gpio 150-134 */
#define GPIO_OUT_7 GPIO1_REG(0x214) /* gpio 181-151 */

/* same pin map as above, output enable */
#define GPIO_OE_0 GPIO1_REG(0x20)
#define GPIO_OE_0 GPIO1_REG(0x10)
#define GPIO_OE_1 GPIO2_REG(0x08)
#define GPIO_OE_2 GPIO1_REG(0x24)
#define GPIO_OE_3 GPIO1_REG(0x28)
#define GPIO_OE_4 GPIO1_REG(0x2C)
#define GPIO_OE_5 GPIO1_REG(0x30)
#define GPIO_OE_6 GPIO1_REG(0x34)
#define GPIO_OE_7 GPIO1_REG(0x38)
#define GPIO_OE_2 GPIO1_REG(0x14)
#define GPIO_OE_3 GPIO1_REG(0x18)
#define GPIO_OE_4 GPIO1_REG(0x1C)
#define GPIO_OE_5 GPIO1_REG(0x54)
#define GPIO_OE_6 GPIO1_REG(0xC8)
#define GPIO_OE_7 GPIO1_REG(0x218)

/* same pin map as above, input read */
#define GPIO_IN_0 GPIO1_REG(0x50)
#define GPIO_IN_0 GPIO1_REG(0x34)
#define GPIO_IN_1 GPIO2_REG(0x20)
#define GPIO_IN_2 GPIO1_REG(0x54)
#define GPIO_IN_3 GPIO1_REG(0x58)
#define GPIO_IN_4 GPIO1_REG(0x5C)
#define GPIO_IN_5 GPIO1_REG(0x60)
#define GPIO_IN_6 GPIO1_REG(0x64)
#define GPIO_IN_7 GPIO1_REG(0x68)
#define GPIO_IN_2 GPIO1_REG(0x38)
#define GPIO_IN_3 GPIO1_REG(0x3C)
#define GPIO_IN_4 GPIO1_REG(0x40)
#define GPIO_IN_5 GPIO1_REG(0x44)
#define GPIO_IN_6 GPIO1_REG(0xCC)
#define GPIO_IN_7 GPIO1_REG(0x21C)

/* same pin map as above, 1=edge 0=level interrup */
#define GPIO_INT_EDGE_0 GPIO1_REG(0x70)
#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
#define GPIO_INT_EDGE_2 GPIO1_REG(0x74)
#define GPIO_INT_EDGE_3 GPIO1_REG(0x78)
#define GPIO_INT_EDGE_4 GPIO1_REG(0x7C)
#define GPIO_INT_EDGE_5 GPIO1_REG(0x80)
#define GPIO_INT_EDGE_6 GPIO1_REG(0x84)
#define GPIO_INT_EDGE_7 GPIO1_REG(0x88)
#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
#define GPIO_INT_EDGE_5 GPIO1_REG(0xC0)
#define GPIO_INT_EDGE_6 GPIO1_REG(0xD0)
#define GPIO_INT_EDGE_7 GPIO1_REG(0x240)

/* same pin map as above, 1=positive 0=negative */
#define GPIO_INT_POS_0 GPIO1_REG(0x90)
#define GPIO_INT_POS_0 GPIO1_REG(0x70)
#define GPIO_INT_POS_1 GPIO2_REG(0x58)
#define GPIO_INT_POS_2 GPIO1_REG(0x94)
#define GPIO_INT_POS_3 GPIO1_REG(0x98)
#define GPIO_INT_POS_4 GPIO1_REG(0x9C)
#define GPIO_INT_POS_5 GPIO1_REG(0xA0)
#define GPIO_INT_POS_6 GPIO1_REG(0xA4)
#define GPIO_INT_POS_7 GPIO1_REG(0xA8)
#define GPIO_INT_POS_2 GPIO1_REG(0x74)
#define GPIO_INT_POS_3 GPIO1_REG(0x78)
#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
#define GPIO_INT_POS_5 GPIO1_REG(0xBC)
#define GPIO_INT_POS_6 GPIO1_REG(0xD4)
#define GPIO_INT_POS_7 GPIO1_REG(0x228)

/* same pin map as above, interrupt enable */
#define GPIO_INT_EN_0 GPIO1_REG(0xB0)
#define GPIO_INT_EN_0 GPIO1_REG(0x80)
#define GPIO_INT_EN_1 GPIO2_REG(0x60)
#define GPIO_INT_EN_2 GPIO1_REG(0xB4)
#define GPIO_INT_EN_3 GPIO1_REG(0xB8)
#define GPIO_INT_EN_4 GPIO1_REG(0xBC)
#define GPIO_INT_EN_5 GPIO1_REG(0xC0)
#define GPIO_INT_EN_6 GPIO1_REG(0xC4)
#define GPIO_INT_EN_7 GPIO1_REG(0xC8)
#define GPIO_INT_EN_2 GPIO1_REG(0x84)
#define GPIO_INT_EN_3 GPIO1_REG(0x88)
#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
#define GPIO_INT_EN_5 GPIO1_REG(0xB8)
#define GPIO_INT_EN_6 GPIO1_REG(0xD8)
#define GPIO_INT_EN_7 GPIO1_REG(0x22C)

/* same pin map as above, write 1 to clear interrupt */
#define GPIO_INT_CLEAR_0 GPIO1_REG(0xD0)
#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
#define GPIO_INT_CLEAR_2 GPIO1_REG(0xD4)
#define GPIO_INT_CLEAR_3 GPIO1_REG(0xD8)
#define GPIO_INT_CLEAR_4 GPIO1_REG(0xDC)
#define GPIO_INT_CLEAR_5 GPIO1_REG(0xE0)
#define GPIO_INT_CLEAR_6 GPIO1_REG(0xE4)
#define GPIO_INT_CLEAR_7 GPIO1_REG(0xE8)
#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
#define GPIO_INT_CLEAR_5 GPIO1_REG(0xB4)
#define GPIO_INT_CLEAR_6 GPIO1_REG(0xDC)
#define GPIO_INT_CLEAR_7 GPIO1_REG(0x230)

/* same pin map as above, 1=interrupt pending */
#define GPIO_INT_STATUS_0 GPIO1_REG(0xF0)
#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
#define GPIO_INT_STATUS_2 GPIO1_REG(0xF4)
#define GPIO_INT_STATUS_3 GPIO1_REG(0xF8)
#define GPIO_INT_STATUS_4 GPIO1_REG(0xFC)
#define GPIO_INT_STATUS_5 GPIO1_REG(0x100)
#define GPIO_INT_STATUS_6 GPIO1_REG(0x103)
#define GPIO_INT_STATUS_7 GPIO1_REG(0x108)
#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
#define GPIO_INT_STATUS_5 GPIO1_REG(0xB0)
#define GPIO_INT_STATUS_6 GPIO1_REG(0xE0)
#define GPIO_INT_STATUS_7 GPIO1_REG(0x234)


#define GPIO_OUT_VAL_REG_BASE 0xABC00000
#define GPIO_ALT_FUNC_PAGE_REG (GPIO_OUT_VAL_REG_BASE + 0x20)
#define GPIO_ALT_FUNC_CFG_REG (GPIO_OUT_VAL_REG_BASE + 0x24)

/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
#define GPIO_OUTPUT 1

/* GPIO TLMM: Pullup/Pulldown */
#define GPIO_NO_PULL 0
#define GPIO_PULL_DOWN 1
#define GPIO_KEEPER 2
#define GPIO_PULL_UP 3

/* GPIO TLMM: Drive Strength */
#define GPIO_2MA 0
#define GPIO_4MA 1
#define GPIO_6MA 2
#define GPIO_8MA 3
#define GPIO_10MA 4
#define GPIO_12MA 5
#define GPIO_14MA 6
#define GPIO_16MA 7

/* GPIO TLMM: Status */
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1

#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
((((gpio) & 0x3FF) << 4) | \
((func) & 0xf) | \
(((dir) & 0x1) << 14) | \
(((pull) & 0x3) << 15) | \
(((drvstr) & 0xF) << 17))

/**
* struct msm_gpio - GPIO pin description
* @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
* @label - textual label
*
* Usually, GPIO's are operated by sets.
* This struct accumulate all GPIO information in single source
* and facilitete group operations provided by msm_gpios_xxx()
*/
struct msm_gpio {
unsigned gpio_cfg;
const char *label;
};

/**
* extract GPIO pin from bit-field used for gpio_tlmm_config
*/
#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff)
#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf)
#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1)
#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3)
#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf)

#endif
9 changes: 7 additions & 2 deletions platform/msm7x30/platform.c
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Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,11 @@ void platform_init(void)

void display_init(void)
{
//fb_cfg = lcdc_init();
//fbcon_setup(fb_cfg);
#if DISPLAY_TYPE_LCDC
struct fbcon_config *fb_cfg;
mdp_clock_init(122880000);
fb_cfg = lcdc_init();
panel_poweron();
fbcon_setup(fb_cfg);
#endif
}
2 changes: 1 addition & 1 deletion platform/msm7x30/rules.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ CPU := generic
MMC_SLOT := 2

DEFINES += WITH_CPU_EARLY_INIT=1 WITH_CPU_WARM_BOOT=1 \
MMC_SLOT=$(MMC_SLOT)
MMC_SLOT=$(MMC_SLOT) MDP4=1

INCLUDES += -I$(LOCAL_DIR)/include

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