makefile added

Makefile

@@ -0,0 +1,33 @@
+COMPILER = ghdl
+WORKDIR = debug
+FLAGS = --ieee=synopsys 
+
+VHDL_SOURCES = $(wildcard rtl/*.vhd)
+TBS = $(wildcard tb/tb_*.vhd)
+UNIT_NAMES=$(basename $(notdir $(TBS)))
+
+.PHONY: all
+all: 	check analyze simulate clean
+			$(info "Completed.")
+
+.PHONY: check
+check: $(info "Checking...")
+	   mkdir -p $(WORKDIR)
+	   $(COMPILER) -s $(FLAGS) --workdir=$(WORKDIR) $(VHDL_SOURCES) $(TBS)
+
+.PHONY: analyze
+analyze: $(info "Analyzing...")
+		 $(COMPILER) -a $(FLAGS) --workdir=$(WORKDIR) $(VHDL_SOURCES) $(TBS)
+
+.PHONY: simulate
+simulate: $(info "Simulating...")
+		  for t in $(UNIT_NAMES); do\
+				$(COMPILER) --elab-run $(FLAGS) --workdir=$(WORKDIR) $$t;\
+		  done;
+
+.PHONY: clean
+clean: $(info "Cleaning...")
+	   $(COMPILER) --remove --workdir=$(WORKDIR)
+	   rm -rf $(WORKDIR)
+	   $(info "Done...")
+

tb/tb_full_adder.vhd

@@ -11,9 +11,9 @@ end entity;
 architecture bench of tb_full_adder is
   component full_adder
     port (
-      x_in, y_in, c_in : in  std_logic;
+      x_in, y_in, c_in : in std_logic;
       s_out, c_out     : out std_logic
-      );
+    );
   end component;
 
   signal x_tb_in  : std_logic;
@@ -28,7 +28,7 @@ begin
 
   process
 
-    file Fin : text open read_mode is "full_adder_input.txt";
+    file Fin : text open read_mode is "tb/full_adder_input.txt";
 
     variable current_read_line   : line;
     variable current_read_field1 : std_logic;
@@ -58,4 +58,4 @@ begin
     end loop;
     wait;
   end process;
-end architecture;
+end architecture;

tb/tb_mux_4to1.vhd

@@ -27,7 +27,7 @@ begin
   DUT : mux_4to1 port map(ABCD_in => ABCD_TB_in, Sel_in => Sel_TB_in, F_out => F_TB_out);
 
   process
-    file Fin : text open read_mode is "mux_4to1_tests.txt";
+    file Fin : text open read_mode is "tb/mux_4to1_tests.txt";
 
     variable current_read_line   : line;
     variable current_read_field1 : std_logic_vector(0 to 3);

tb/tb_onehot_decoder_3to8.vhd

@@ -25,7 +25,7 @@ begin
   DUT : onehot_decoder_3to8 port map(ABC_in => ABC_TB_in, F_out => F_TB_out);
 
   process
-    file Fin  : text open read_mode is "onehot_decoder_3to8_input.txt";
+    file Fin  : text open read_mode is "tb/onehot_decoder_3to8_input.txt";
     file Fout : text open write_mode is "onehot_decoder_3to8_output.txt";
 
     variable current_read_line  : line;

tb/tb_sop_circuit.vhd

@@ -25,7 +25,7 @@ begin
   DUT : sop_circuit port map(ABC_in => ABC_TB_in, F_out => F_TB_out);
 
   process
-    file Fin  : text open read_mode is "sop_circuit_input.txt";
+    file Fin  : text open read_mode is "tb/sop_circuit_input.txt";
     file Fout : text open write_mode is "sop_circuit_output.txt";
 
     variable current_read_line  : line;