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[dvsim,hjson] Remove all dead code 'design_level' references/overrides #27486

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Merged
hcallahan-lowrisc merged 1 commit into from
Jun 27, 2025
Merged

[dvsim,hjson] Remove all dead code 'design_level' references/overrides #27486

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1 change: 0 additions & 1 deletion hw/cdc/tools/dvsim/common_cdc_cfg.hjson
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Expand Up @@ -31,7 +31,6 @@
"{fusesoc_core}"]
sv_flist_gen_dir: "{build_dir}/syn-icarus"
sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
sv_flist_gen_flags: ["--flag=fileset_{design_level}"]

// Determines which message severities to print into report summaries.
report_severities: ["review", "warning", "error"]
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3 changes: 0 additions & 3 deletions hw/data/common_project_cfg.hjson
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Expand Up @@ -41,7 +41,4 @@
printf "<br>$REV_STR_FOUNDRY"; \
fi
'''

// The current design level
design_level: "ip"
}
3 changes: 1 addition & 2 deletions hw/dv/tools/dvsim/common_sim_cfg.hjson
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Expand Up @@ -13,8 +13,7 @@
"{dv_root}/tools/dvsim/bazel.hjson",
"{dv_root}/tools/dvsim/{tool}.hjson"]

sv_flist_gen_flags: ["--flag=fileset_{design_level}",
"--mapping=lowrisc:prim_generic:all:0.1"]
sv_flist_gen_flags: ["--mapping=lowrisc:prim_generic:all:0.1"]
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@a-will a-will Jun 23, 2025

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We probably ought to move this to a less-generic property name, so people can override mappings more explicitly. Fine for now, though! (especially since there are only mappings here right now)

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@hcallahan-lowrisc hcallahan-lowrisc Jun 27, 2025

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Yeah, maybe something like a fusesoc_mapping_cores list could be used, with the eval_cmd trick...

  sv_flist_gen_opts:  ["{fusesoc_cores_root_dirs}",
                       "run",
                       "{sv_flist_gen_flags}",
                       "--target=sim",
                       "--build-root={build_dir}",
                       "--setup,
                       # Something like this...
                       "{eval_cmd} echo \"{fusesoc_mapping_cores}\" | sed -E 's_(\\S+)_\"--mapping=\\1\"_g",
                       {fusesoc_core}"]


// Default directory structure for the output
build_dir: "{scratch_path}/{build_mode}"
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1 change: 0 additions & 1 deletion hw/dv/tools/dvsim/fusesoc.hjson
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Expand Up @@ -13,5 +13,4 @@
fusesoc_cores_root_dirs: ["--cores-root {proj_root}/hw"]
sv_flist_gen_dir: "{build_dir}/fusesoc-work"
sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
sv_flist_gen_flags: ["--flag=fileset_{design_level}"]
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@a-will a-will Jun 23, 2025

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A curiosity: How should we document that this property exists, that it is an array of strings, and that it should be used to pass arguments to fusesoc run?

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@hcallahan-lowrisc hcallahan-lowrisc Jun 27, 2025

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I'm personally leaning towards leading by example here. Some pages documenting how this can be done, with example .hjson and accompanying comments. Maybe in the future a proper schema for dvsim .hjson would be a useful addition as well, but it is probably a bit too complex to decipher without a worked example or reference pointing to existing code.

}
3 changes: 1 addition & 2 deletions hw/dv/tools/dvsim/verilator.hjson
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Expand Up @@ -51,8 +51,7 @@
// TODO: Verilator has a few useful build switches. Need to figure out how to
// pass them via FuseSoC.

build_opts: ["--flag=fileset_{design_level}",
"--target=sim",
build_opts: ["--target=sim",
"--build-root={build_dir}",
"--setup",
"--build",
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6 changes: 0 additions & 6 deletions hw/formal/tools/dvsim/common_conn_cfg.hjson
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Expand Up @@ -12,12 +12,6 @@
]

overrides: [
// Connectivity test should all be in top_level design
{
name: design_level
value: "top"
}

// Connectivity test won't run any assertions, so here we use default RTL target
{
name: fusesoc_target
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3 changes: 1 addition & 2 deletions hw/formal/tools/dvsim/common_formal_cfg.hjson
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Expand Up @@ -30,8 +30,7 @@
"--work-root={build_dir}/fusesoc-work",
"--setup {fusesoc_core}"]
sv_flist_gen_dir: "{build_dir}/fusesoc-work"
sv_flist_gen_flags: ["--flag=fileset_{design_level}",
"--mapping=lowrisc:prim_generic:all:0.1"]
sv_flist_gen_flags: ["--mapping=lowrisc:prim_generic:all:0.1"]

report_cmd: "python3 {formal_root}/tools/{tool}/parse-formal-report.py"
report_opts: ["--logpath={build_log}",
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4 changes: 0 additions & 4 deletions hw/ip/lc_ctrl/syn/lc_ctrl_gtech_syn_cfg.hjson
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"{proj_root}/hw/syn/tools/dvsim/common_gtech_syn_cfg.hjson"]

overrides: [
{
name: design_level
value: "top"
}
{ // Deletes black-boxed hierarchies before writing out the unmapped netlist
name: post_elab_script
value: "{proj_root}/hw/ip/{name}/syn/post_elab_gtech.tcl"
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7 changes: 0 additions & 7 deletions hw/ip/lc_ctrl/syn/lc_ctrl_syn_cfg.hjson
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Expand Up @@ -11,13 +11,6 @@
import_cfgs: [// Project wide common synthesis config file
"{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"]

overrides: [
{
name: design_level
value: "top"
}
]

// Timing constraints for this module
sdc_file: "{proj_root}/hw/ip/{name}/syn/constraints.sdc"

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4 changes: 0 additions & 4 deletions hw/ip_templates/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson.tpl
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en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"]
// Flash references pwrmgr directly, need to reference the top version
overrides: [
{
name: design_level
value: "top"
}
{
name: "timescale"
value: "1ns/100ps"
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4 changes: 0 additions & 4 deletions hw/ip_templates/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson.tpl
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"{proj_root}/hw/syn/tools/dvsim/common_gtech_syn_cfg.hjson"]

overrides: [
{
name: design_level
value: "top"
}
{ // Deletes black-boxed hierarchies before writing out the unmapped netlist
name: post_elab_script
value: "{proj_root}/hw/top_${topname}/ip_autogen/{name}/syn/post_elab_gtech.tcl"
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7 changes: 0 additions & 7 deletions hw/ip_templates/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson.tpl
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Expand Up @@ -11,13 +11,6 @@
import_cfgs: [// Project wide common synthesis config file
"{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"]

overrides: [
{
name: design_level
value: "top"
}
]

// Timing constraints for this module
sdc_file: "{proj_root}/hw/top_${topname}/ip_autogen/{name}/syn/constraints.sdc"

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4 changes: 0 additions & 4 deletions hw/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl
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// Overrides
overrides: [
{
name: design_level
value: "top"
}
// Handle generated coverage exclusion.
{
name: default_vcs_cov_cfg_file
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7 changes: 0 additions & 7 deletions hw/ip_templates/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson.tpl
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tests: ["rstmgr_cnsty_chk_test"]
}
]
overrides: [
// This override is in order to pick the autogen rstmgr packages.
{
name: design_level
value: "top"
}
]
}
4 changes: 0 additions & 4 deletions hw/ip_templates/rstmgr/dv/rstmgr_sim_cfg.hjson.tpl
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// Overrides
overrides: [
{
name: design_level
value: "top"
}
{
name: default_vcs_cov_cfg_file
value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/rstmgr_cover.cfg+{self_dir}/cov/rstmgr_tgl_excl.cfg"
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1 change: 0 additions & 1 deletion hw/lint/tools/dvsim/common_lint_cfg.hjson
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Expand Up @@ -22,7 +22,6 @@
build_cmd: "{job_prefix} fusesoc"
build_opts: ["--cores-root {proj_root}/hw",
"run",
"--flag=fileset_{design_level}",
"--target={flow}",
"--tool={tool}",
"--work-root={build_dir}/fusesoc-work",
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1 change: 0 additions & 1 deletion hw/rdc/tools/dvsim/common_rdc_cfg.hjson
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Expand Up @@ -31,7 +31,6 @@
"{fusesoc_core}"]
sv_flist_gen_dir: "{build_dir}/syn-icarus"
sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
sv_flist_gen_flags: ["--flag=fileset_{design_level}"]

// Determines which message severities to print into report summaries.
report_severities: ["review", "warning", "error"]
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1 change: 0 additions & 1 deletion hw/syn/tools/dvsim/common_syn_cfg.hjson
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"{fusesoc_core}"]
sv_flist_gen_dir: "{build_dir}/syn-icarus"
sv_flist: "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
sv_flist_gen_flags: ["--flag=fileset_{design_level}"]

// Can be used to hook in an additional post elab scripting step.
post_elab_script: ""
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4 changes: 0 additions & 4 deletions hw/top_darjeeling/data/chip_cfg.hjson
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Expand Up @@ -15,9 +15,5 @@
"--cores-root {proj_root}/hw/vendor",
"--cores-root {proj_root}/hw/top_darjeeling"]
}
{
name: design_level
value: "top"
}
]
}
1 change: 0 additions & 1 deletion hw/top_darjeeling/dv/chip_sim_cfg.hjson
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Expand Up @@ -59,7 +59,6 @@
"{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson",
"{proj_root}/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson",
"{proj_root}/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson",
// This defines the design_level: "top" key
// "{proj_root}/hw/{top_chip}/data/chip_cfg.hjson",
"{top_dv_path}/chip_smoketests.hjson",
"{top_dv_path}/chip_rom_tests.hjson",
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12 changes: 0 additions & 12 deletions hw/top_darjeeling/formal/top_darjeeling_fpv_ip_cfgs.hjson
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Expand Up @@ -40,12 +40,6 @@
defines: "FPV_ALERT_NO_SIGINT_ERR"
cov: true
exp_fail_hjson: "{proj_root}/hw/{top_chip}/ip/pinmux/fpv/pinmux_expected_failure.hjson"
overrides: [
{
name: design_level
value: "top"
}
]
}

{
Expand All @@ -56,12 +50,6 @@
rel_path: "hw/{top_chip}/ip_autogen/rv_plic/{sub_flow}/{tool}"
cov: true
exp_fail_hjson: "{proj_root}/hw/{top_chip}/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson"
overrides: [
{
name: design_level
value: "top"
}
]
}
]
}
36 changes: 0 additions & 36 deletions hw/top_darjeeling/formal/top_darjeeling_fpv_sec_cm_cfgs.hjson
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Expand Up @@ -82,12 +82,6 @@
fusesoc_core: lowrisc:dv:top_darjeeling_flash_ctrl_sva
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
rel_path: "hw/ip/flash_ctrl/{sub_flow}/{tool}"
overrides: [
{
name: design_level
value: "top"
}
]
stopats: ["*u_state_regs.state_o", "*u_rma_state_regs.state_o"]
task: "FpvSecCm"
}
Expand Down Expand Up @@ -145,12 +139,6 @@
fusesoc_core: lowrisc:dv:top_darjeeling_pwrmgr_sva
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
rel_path: "hw/ip/pwrmgr/{sub_flow}/{tool}"
overrides: [
{
name: design_level
value: "top"
}
]
stopats: ["*u_state_regs.state_o"]
task: "FpvSecCm"
}
Expand All @@ -169,12 +157,6 @@
fusesoc_core: lowrisc:dv:top_darjeeling_rstmgr_sva
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
rel_path: "hw/ip/rstmgr/{sub_flow}/{tool}"
overrides: [
{
name: design_level
value: "top"
}
]
stopats: ["*u_state_regs.state_o"]
task: "FpvSecCm"
}
Expand Down Expand Up @@ -210,12 +192,6 @@
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
rel_path: "hw/{top_chip}/ip/pinmux/{sub_flow}/{tool}/sec_cm"
task: "FpvSecCm"
overrides: [
{
name: design_level
value: "top"
}
]
}
{
name: rv_plic_sec_cm
Expand All @@ -224,12 +200,6 @@
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
rel_path: "hw/{top_chip}/ip/rv_plic/{sub_flow}/{tool}/sec_cm"
task: "FpvSecCm"
overrides: [
{
name: design_level
value: "top"
}
]
}

// Other non-standard countermeasure checks.
Expand Down Expand Up @@ -273,12 +243,6 @@
fusesoc_core: lowrisc:dv:top_darjeeling_pwrmgr_sva
import_cfgs: ["{proj_root}/hw/formal/tools/dvsim/common_fpv_cfg.hjson"]
rel_path: "hw/ip/pwrmgr/{sub_flow}/{tool}"
overrides: [
{
name: design_level
value: "top"
}
]
task: "PwrmgrSecCmEsc"
}
]
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4 changes: 0 additions & 4 deletions hw/top_darjeeling/ip_autogen/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson
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"{proj_root}/hw/syn/tools/dvsim/common_gtech_syn_cfg.hjson"]

overrides: [
{
name: design_level
value: "top"
}
{ // Deletes black-boxed hierarchies before writing out the unmapped netlist
name: post_elab_script
value: "{proj_root}/hw/top_darjeeling/ip_autogen/{name}/syn/post_elab_gtech.tcl"
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7 changes: 0 additions & 7 deletions hw/top_darjeeling/ip_autogen/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson
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import_cfgs: [// Project wide common synthesis config file
"{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"]

overrides: [
{
name: design_level
value: "top"
}
]

// Timing constraints for this module
sdc_file: "{proj_root}/hw/top_darjeeling/ip_autogen/{name}/syn/constraints.sdc"

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4 changes: 0 additions & 4 deletions hw/top_darjeeling/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson
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// Overrides
overrides: [
{
name: design_level
value: "top"
}
// Handle generated coverage exclusion.
{
name: default_vcs_cov_cfg_file
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7 changes: 0 additions & 7 deletions hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson
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tests: ["rstmgr_cnsty_chk_test"]
}
]
overrides: [
// This override is in order to pick the autogen rstmgr packages.
{
name: design_level
value: "top"
}
]
}
4 changes: 0 additions & 4 deletions hw/top_darjeeling/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
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// Overrides
overrides: [
{
name: design_level
value: "top"
}
{
name: default_vcs_cov_cfg_file
value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/rstmgr_cover.cfg+{self_dir}/cov/rstmgr_tgl_excl.cfg"
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6 changes: 0 additions & 6 deletions hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson
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Expand Up @@ -214,12 +214,6 @@
// fusesoc_core: lowrisc:dv:top_darjeeling_chip_sim
// import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
// rel_path: "hw/top_darjeeling/dv/lint/{tool}"
// overrides: [
// {
// name: design_level
// value: "top"
// }
// ]
// },
]
}
6 changes: 0 additions & 6 deletions hw/top_darjeeling/lint/top_darjeeling_fpga_lint_cfgs.hjson
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Expand Up @@ -24,12 +24,6 @@
// fusesoc_core: lowrisc:systems:chip_darjeeling_cw310
// import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
// rel_path: "hw/chip_darjeeling_asic/lint/{tool}"
// overrides: [
// {
// name: design_level
// value: "top"
// }
// ]
// },
]

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