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[RISCV] Add Tied operands in Xqcicm instructions and changes to handle a single tied operand in source DAG and instruction #145538

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Jun 25, 2025
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15 changes: 9 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
Original file line number Diff line number Diff line change
Expand Up @@ -596,17 +596,20 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class QCIMVCC<bits<3> funct3, string opcodestr>
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd),
(ins GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
opcodestr, "$rd, $rs1, $rs2, $rs3">;
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
opcodestr, "$rd, $rs1, $rs2, $rs3"> {
let Constraints = "$rd = $rd_wb";
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd),
(ins GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),
opcodestr, "$rd, $rs1, $imm, $rs3"> {
bits<5> imm;


let Constraints = "$rd = $rd_wb";
let rs2 = imm;
}

Expand Down
6 changes: 6 additions & 0 deletions llvm/test/MC/RISCV/xqcicm-valid.s
Original file line number Diff line number Diff line change
Expand Up @@ -135,3 +135,9 @@ qc.mveqi x9, x9, 0, x12
# CHECK-ENC: encoding: [0x06,0xae]
qc.mvltui x9, x9, 1, x12

# Following instruction should not be compressed

# CHECK-INST: qc.mveqi a0, s1, 0, a2
# CHECK-ENC: encoding: [0x5b,0x85,0x04,0x64]
qc.mveqi x10, x9, 0, x12

15 changes: 11 additions & 4 deletions llvm/utils/TableGen/CompressInstEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -137,7 +137,8 @@ class CompressInstEmitter {
StringMap<unsigned> &SourceOperands,
StringMap<unsigned> &DestOperands,
const DagInit *SourceDag, const DagInit *DestDag,
IndexedMap<OpData> &SourceOperandMap);
IndexedMap<OpData> &SourceOperandMap,
bool HasSourceTiedOp);

void createInstOperandMapping(const Record *Rec, const DagInit *SourceDag,
const DagInit *DestDag,
Expand Down Expand Up @@ -349,7 +350,8 @@ static bool validateArgsTypes(const Init *Arg1, const Init *Arg2) {
void CompressInstEmitter::createDagOperandMapping(
const Record *Rec, StringMap<unsigned> &SourceOperands,
StringMap<unsigned> &DestOperands, const DagInit *SourceDag,
const DagInit *DestDag, IndexedMap<OpData> &SourceOperandMap) {
const DagInit *DestDag, IndexedMap<OpData> &SourceOperandMap,
bool HasSourceTiedOp) {
for (unsigned I = 0; I < DestDag->getNumArgs(); ++I) {
// Skip fixed immediates and registers, they were handled in
// addDagOperandMapping.
Expand All @@ -368,7 +370,10 @@ void CompressInstEmitter::createDagOperandMapping(
SourceOperands.find(SourceDag->getArgNameStr(I));
if (It != SourceOperands.end()) {
// Operand sharing the same name in the Dag should be mapped as tied.
SourceOperandMap[I].TiedOpIdx = It->getValue();
if (HasSourceTiedOp)
SourceOperandMap[I + 1].TiedOpIdx = It->getValue() + 1;
else
SourceOperandMap[I].TiedOpIdx = It->getValue();
if (!validateArgsTypes(SourceDag->getArg(It->getValue()),
SourceDag->getArg(I)))
PrintFatalError(Rec->getLoc(),
Expand Down Expand Up @@ -521,8 +526,10 @@ void CompressInstEmitter::evaluateCompressPat(const Record *Rec) {

StringMap<unsigned> SourceOperands;
StringMap<unsigned> DestOperands;
bool HasSourceTiedOp =
SourceLastTiedOp != std::numeric_limits<unsigned int>::max();
createDagOperandMapping(Rec, SourceOperands, DestOperands, SourceDag, DestDag,
SourceOperandMap);
SourceOperandMap, HasSourceTiedOp);
// Create operand mapping between the source and destination instructions.
createInstOperandMapping(Rec, SourceDag, DestDag, SourceOperandMap,
DestOperandMap, SourceOperands, DestInst,
Expand Down
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