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[llvm] Optimize misaligned accesses with early profitable splitting #145168

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138 changes: 138 additions & 0 deletions llvm/lib/CodeGen/CodeGenPrepare.cpp
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Expand Up @@ -436,6 +436,8 @@ class CodeGenPrepare {
bool optimizeExt(Instruction *&I);
bool optimizeExtUses(Instruction *I);
bool optimizeLoadExt(LoadInst *Load);
bool optimizeStoreMisalign(StoreInst *ST);
bool optimizeLoadMisalign(LoadInst *ST);
bool optimizeShiftInst(BinaryOperator *BO);
bool optimizeFunnelShift(IntrinsicInst *Fsh);
bool optimizeSelectInst(SelectInst *SI);
Expand Down Expand Up @@ -7353,6 +7355,138 @@ bool CodeGenPrepare::optimizeLoadExt(LoadInst *Load) {
return true;
}

static bool isOptimizeMisalignCandidate(Instruction *I, const DataLayout *DL,
const TargetLowering *TLI,
const DominatorTree *DT) {
if (!isa<StoreInst>(I) && !isa<LoadInst>(I))
return false;

Value *Ptr = I->getOperand(isa<StoreInst>(I) ? 1 : 0);
Align Alignment = isa<StoreInst>(I) ? cast<StoreInst>(I)->getAlign()
: cast<LoadInst>(I)->getAlign();
Type *ValTy = isa<StoreInst>(I) ? I->getOperand(0)->getType() : I->getType();

if (ValTy->isScalableTy() || !ValTy->isSized())
return false;

unsigned BitWidth = DL->getTypeSizeInBits(ValTy);

// DAG legalization can handle this situation well
if (Alignment.value() * 8 >= BitWidth / 2)
return false;

Type *PtrTy = Ptr->getType();
EVT ValVT = TLI->getValueType(*DL, ValTy, true);
if (!ValVT.isSimple() || ValVT == MVT::Other ||
TLI->allowsMisalignedMemoryAccesses(
ValVT, PtrTy->getPointerAddressSpace(), Alignment))
return false;

KnownBits Known = computeKnownBits(Ptr, *DL, nullptr, I, DT);
if (Known.isUnknown())
return false;

unsigned PtrWidth = DL->getPointerTypeSizeInBits(PtrTy);
KnownBits AlignKnown =
KnownBits::makeConstant(APInt(PtrWidth, Alignment.value()));

if (KnownBits::add(Known, AlignKnown).countMinTrailingZeros() <=
AlignKnown.countMinTrailingZeros())
return false;
return true;
}

bool CodeGenPrepare::optimizeStoreMisalign(StoreInst *SI) {
if (!isOptimizeMisalignCandidate(SI, DL, TLI, DT.get()))
return false;

IRBuilder<> Builder(SI);
Value *Val = SI->getValueOperand();
unsigned BitWidth = DL->getTypeSizeInBits(Val->getType());
if (!Val->getType()->isIntegerTy())
Val =
Builder.CreateBitCast(Val, Type::getIntNTy(SI->getContext(), BitWidth));

bool IsLE = DL->isLittleEndian();
bool IsVolatile = SI->isVolatile();
Align Alignment = SI->getAlign();
Value *Ptr = SI->getPointerOperand();
unsigned RemainingBits = BitWidth;
Type *Int8Ty = Type::getInt8Ty(SI->getContext());
Type *Int32Ty = Type::getInt32Ty(SI->getContext());

while (RemainingBits > 0) {
unsigned ChunkBits =
std::min((uint64_t)(RemainingBits), 8 * Alignment.value());
Type *ChunkTy = Type::getIntNTy(SI->getContext(), ChunkBits);
Value *ChunkVal;
if (IsLE) {
ChunkVal = Builder.CreateTrunc(Val, ChunkTy);
} else {
Value *ShiftR = Builder.CreateLShr(Val, BitWidth - ChunkBits);
ChunkVal = Builder.CreateTrunc(ShiftR, ChunkTy);
}
Builder.CreateAlignedStore(ChunkVal, Ptr, Alignment, IsVolatile);
RemainingBits -= ChunkBits;
if (RemainingBits == 0)
break;

Val = IsLE ? Builder.CreateLShr(Val, ChunkBits)
: Builder.CreateShl(Val, ChunkBits);
Ptr = Builder.CreateGEP(Int8Ty, Ptr,
ConstantInt::get(Int32Ty, ChunkBits / 8));
Alignment = getKnownAlignment(Ptr, *DL);
}

SI->eraseFromParent();
return true;
}

bool CodeGenPrepare::optimizeLoadMisalign(LoadInst *LI) {
if (!isOptimizeMisalignCandidate(LI, DL, TLI, DT.get()))
return false;

IRBuilder<> Builder(LI);
Type *ValTy = LI->getType();

unsigned BitWidth = DL->getTypeSizeInBits(LI->getType());
bool IsLE = DL->isLittleEndian();
bool IsVolatile = LI->isVolatile();
Align Alignment = LI->getAlign();
Value *Ptr = LI->getPointerOperand();
unsigned RemainingBits = BitWidth;
Type *IntTy = Type::getIntNTy(LI->getContext(), BitWidth);
Type *Int8Ty = Type::getInt8Ty(LI->getContext());
Type *Int32Ty = Type::getInt32Ty(LI->getContext());
Value *Val = ConstantInt::get(IntTy, 0);

while (RemainingBits > 0) {
unsigned ChunkBits =
std::min((uint64_t)(RemainingBits), 8 * Alignment.value());
Type *ChunkTy = Type::getIntNTy(LI->getContext(), ChunkBits);
Value *ChunkVal = Builder.CreateZExt(
Builder.CreateAlignedLoad(ChunkTy, Ptr, Alignment, IsVolatile), IntTy);
if (IsLE) {
ChunkVal = Builder.CreateShl(ChunkVal, BitWidth - RemainingBits);
} else {
ChunkVal = Builder.CreateShl(Val, RemainingBits - ChunkBits);
}
Val = Builder.CreateOr(Val, ChunkVal);
RemainingBits -= ChunkBits;
if (RemainingBits == 0)
break;
Ptr = Builder.CreateGEP(Int8Ty, Ptr,
ConstantInt::get(Int32Ty, ChunkBits / 8));
Alignment = getKnownAlignment(Ptr, *DL);
}

if (!ValTy->isIntegerTy())
Val = Builder.CreateBitCast(Val, ValTy);
LI->replaceAllUsesWith(Val);
LI->eraseFromParent();
return true;
}

/// Check if V (an operand of a select instruction) is an expensive instruction
/// that is only used once.
static bool sinkSelectOperand(const TargetTransformInfo *TTI, Value *V) {
Expand Down Expand Up @@ -8750,6 +8884,8 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) {
return true;

if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
if (optimizeLoadMisalign(LI))
return true;
LI->setMetadata(LLVMContext::MD_invariant_group, nullptr);
bool Modified = optimizeLoadExt(LI);
unsigned AS = LI->getPointerAddressSpace();
Expand All @@ -8760,6 +8896,8 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) {
if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
if (splitMergedValStore(*SI, *DL, *TLI))
return true;
if (optimizeStoreMisalign(SI))
return true;
SI->setMetadata(LLVMContext::MD_invariant_group, nullptr);
unsigned AS = SI->getPointerAddressSpace();
return optimizeMemoryInst(I, SI->getOperand(1),
Expand Down
70 changes: 24 additions & 46 deletions llvm/test/CodeGen/AMDGPU/ds_read2.ll
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Expand Up @@ -1451,63 +1451,41 @@ define amdgpu_ps <2 x float> @ds_read_interp_read(i32 inreg %prims, ptr addrspac
define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out) {
; CI-LABEL: read2_v2i32_align1_odd_offset:
; CI: ; %bb.0: ; %entry
; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_read_u8 v1, v0 offset:70
; CI-NEXT: ds_read_u8 v2, v0 offset:72
; CI-NEXT: ds_read_u8 v3, v0 offset:71
; CI-NEXT: ds_read_u8 v4, v0 offset:69
; CI-NEXT: ds_read_u8 v5, v0 offset:68
; CI-NEXT: s_waitcnt lgkmcnt(4)
; CI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; CI-NEXT: s_waitcnt lgkmcnt(3)
; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; CI-NEXT: s_waitcnt lgkmcnt(2)
; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: s_waitcnt lgkmcnt(1)
; CI-NEXT: v_or_b32_e32 v1, v1, v4
; CI-NEXT: ds_read_u8 v4, v0 offset:66
; CI-NEXT: ds_read_u8 v6, v0 offset:67
; CI-NEXT: ds_read_u8 v0, v0 offset:65
; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; CI-NEXT: ds_read_u8 v2, v1 offset:65
; CI-NEXT: ds_read_u16 v3, v1 offset:66
; CI-NEXT: ds_read_b32 v0, v1 offset:68
; CI-NEXT: ds_read_u8 v4, v1 offset:72
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: v_or_b32_e32 v1, v2, v1
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
; CI-NEXT: v_or_b32_e32 v0, v2, v0
; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v5
; CI-NEXT: v_or_b32_e32 v2, v2, v6
; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; CI-NEXT: v_lshl_b64 v[0:1], v[0:1], 24
; CI-NEXT: v_or_b32_e32 v2, v2, v3
; CI-NEXT: v_or_b32_e32 v0, v0, v2
; CI-NEXT: v_lshlrev_b32_e32 v2, 24, v4
; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: v_or_b32_e32 v0, v2, v0
; CI-NEXT: v_or_b32_e32 v1, v1, v2
; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; CI-NEXT: s_endpgm
;
; GFX9-ALIGNED-LABEL: read2_v2i32_align1_odd_offset:
; GFX9-ALIGNED: ; %bb.0: ; %entry
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v2, 0
; GFX9-ALIGNED-NEXT: ds_read_u8 v0, v2 offset:65
; GFX9-ALIGNED-NEXT: ds_read_u8 v3, v2 offset:66
; GFX9-ALIGNED-NEXT: ds_read_u8 v4, v2 offset:67
; GFX9-ALIGNED-NEXT: ds_read_u8 v5, v2 offset:68
; GFX9-ALIGNED-NEXT: ds_read_u8 v1, v2 offset:70
; GFX9-ALIGNED-NEXT: ds_read_u8 v6, v2 offset:69
; GFX9-ALIGNED-NEXT: ds_read_u8 v7, v2 offset:72
; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v2 offset:71
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v1, 0
; GFX9-ALIGNED-NEXT: ds_read_u16 v2, v1 offset:66
; GFX9-ALIGNED-NEXT: ds_read_b32 v0, v1 offset:68
; GFX9-ALIGNED-NEXT: ds_read_u8 v4, v1 offset:65
; GFX9-ALIGNED-NEXT: ds_read_u8 v5, v1 offset:72
; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v1, v6
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v6, 8, v7
; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v5
; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v6, v1
; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-ALIGNED-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v6, 8, v2
; GFX9-ALIGNED-NEXT: v_lshlrev_b64 v[2:3], 24, v[0:1]
; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v0, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-ALIGNED-NEXT: v_or_b32_e32 v2, v0, v2
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v0, 24, v5
; GFX9-ALIGNED-NEXT: v_or_b32_e32 v3, v3, v0
; GFX9-ALIGNED-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]
; GFX9-ALIGNED-NEXT: s_endpgm
;
; GFX9-UNALIGNED-LABEL: read2_v2i32_align1_odd_offset:
Expand Down
22 changes: 6 additions & 16 deletions llvm/test/CodeGen/AMDGPU/ds_write2.ll
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Expand Up @@ -1009,31 +1009,21 @@ define amdgpu_kernel void @write2_v2i32_align1_odd_offset() {
; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_write_b8 v1, v0 offset:65
; CI-NEXT: v_mov_b32_e32 v0, 1
; CI-NEXT: ds_write_b8 v1, v0 offset:70
; CI-NEXT: v_mov_b32_e32 v0, 0xc8
; CI-NEXT: ds_write_b8 v1, v0 offset:69
; CI-NEXT: ds_write_b8 v1, v1 offset:68
; CI-NEXT: ds_write_b8 v1, v1 offset:67
; CI-NEXT: ds_write_b8 v1, v1 offset:66
; CI-NEXT: ds_write_b16 v1, v1 offset:66
; CI-NEXT: v_mov_b32_e32 v0, 0x1c800
; CI-NEXT: ds_write_b32 v1, v0 offset:68
; CI-NEXT: ds_write_b8 v1, v1 offset:72
; CI-NEXT: ds_write_b8 v1, v1 offset:71
; CI-NEXT: s_endpgm
;
; GFX9-ALIGNED-LABEL: write2_v2i32_align1_odd_offset:
; GFX9-ALIGNED: ; %bb.0: ; %entry
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v1, 0
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v0 offset:65
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v0, 1
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v0 offset:70
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v0, 0xc8
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v0 offset:69
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:68
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:67
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:66
; GFX9-ALIGNED-NEXT: ds_write_b16 v1, v1 offset:66
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v0, 0x1c800
; GFX9-ALIGNED-NEXT: ds_write_b32 v1, v0 offset:68
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:72
; GFX9-ALIGNED-NEXT: ds_write_b8 v1, v1 offset:71
; GFX9-ALIGNED-NEXT: s_endpgm
;
; GFX9-UNALIGNED-LABEL: write2_v2i32_align1_odd_offset:
Expand Down
11 changes: 8 additions & 3 deletions llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
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Expand Up @@ -12,10 +12,15 @@ define void @ret_void_args_i8_i32(i8 %a, i32 %b) {
; CHECK: sts 4, r24
store volatile i8 %a, ptr inttoptr (i64 4 to ptr)

; CHECK-NEXT: sts 8, r23
; CHECK-NEXT: sts 7, r22
; CHECK-NEXT: sts 6, r21
; CHECK-NEXT: sts 5, r20

; redundant instructions, should be deleted
; CHECK-NEXT: mov r24, r21
; CHECK-NEXT: mov r25, r22

; CHECK-NEXT: sts 7, r25
; CHECK-NEXT: sts 6, r24
; CHECK-NEXT: sts 8, r23
store volatile i32 %b, ptr inttoptr (i64 5 to ptr)
ret void
}
Expand Down
30 changes: 20 additions & 10 deletions llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,15 @@ start:
%0 = extractvalue { i8, i32 } %a, 0
store volatile i8 %0, ptr inttoptr (i64 4 to ptr)

; CHECK-NEXT: sts 8, r24
; CHECK-NEXT: sts 7, r23
; CHECK-NEXT: sts 6, r22
; CHECK-NEXT: sts 5, r21

; redundant instructions, should be deleted
; CHECK-NEXT: mov r18, r22
; CHECK-NEXT: mov r19, r23

; CHECK-NEXT: sts 7, r19
; CHECK-NEXT: sts 6, r18
; CHECK-NEXT: sts 8, r24
%1 = extractvalue { i8, i32 } %a, 1
store volatile i32 %1, ptr inttoptr (i64 5 to ptr)
ret void
Expand Down Expand Up @@ -62,17 +67,22 @@ start:
%0 = extractvalue { i8, i32 } %a, 0
store volatile i8 %0, ptr inttoptr (i64 4 to ptr)

; CHECK-NEXT: sts 8, r24
; CHECK-NEXT: sts 7, r23
; CHECK-NEXT: sts 6, r22
; CHECK-NEXT: sts 5, r21

; redundant instructions, should be deleted
; CHECK-NEXT: mov r20, r22
; CHECK-NEXT: mov r21, r23

; CHECK-NEXT: sts 7, r21
; CHECK-NEXT: sts 6, r20
; CHECK-NEXT: sts 8, r24
%1 = extractvalue { i8, i32 } %a, 1
store volatile i32 %1, ptr inttoptr (i64 5 to ptr)

; CHECK-NEXT: sts 9, r17
; CHECK-NEXT: sts 8, r16
; CHECK-NEXT: sts 7, r15
; CHECK-NEXT: sts 6, r14
; CHECK-NEXT: sts 9, r17
; CHECK-NEXT: sts 8, r16
; CHECK-NEXT: sts 7, r15
; CHECK-NEXT: sts 6, r14
%2 = extractvalue { i32, i8 } %b, 0
store volatile i32 %2, ptr inttoptr (i64 6 to ptr)

Expand Down
7 changes: 5 additions & 2 deletions llvm/test/CodeGen/XCore/unaligned_load.ll
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Expand Up @@ -24,8 +24,11 @@ entry:

; Constant offset from word aligned base.
; CHECK-LABEL: align3:
; CHECK: ldw {{r[0-9]+}}, dp
; CHECK: ldw {{r[0-9]+}}, dp
; CHECK: ldaw {{r[0-9]+}}, dp
; CHECK: ld8u
; CHECK: ld16s
; CHECK: or
; CHECK: ld8u
; CHECK: or
define i32 @align3() nounwind {
entry:
Expand Down
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