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[CIR][Lowering] Fix Vector Comparison Lowering with -fno-signed-char/unsigned operand #1770

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[CIR][Lowering] Fix Vector Comparison Lowering with -fno-signed-char/unsigned operand #1770

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17 changes: 16 additions & 1 deletion clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2052,9 +2052,24 @@ mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite(
auto elementType = elementTypeIfVector(op.getLhs().getType());
mlir::Value bitResult;
if (auto intType = mlir::dyn_cast<cir::IntType>(elementType)) {

auto isCIRZeroVector = [](mlir::Value value) {
if (auto constantOp = value.getDefiningOp<cir::ConstantOp>())
if (auto zeroAttr =
mlir::dyn_cast<cir::ZeroAttr>(constantOp.getValue()))
return true;
return false;
};

bool shouldUseSigned = intType.isSigned();
// Special treatment for sign-bit extraction patterns (lt comparison with
// zero), always use signed comparison to preserve the semantic intent
if (op.getKind() == cir::CmpOpKind::lt && isCIRZeroVector(op.getRhs()))
shouldUseSigned = true;

bitResult = rewriter.create<mlir::LLVM::ICmpOp>(
op.getLoc(),
convertCmpKindToICmpPredicate(op.getKind(), intType.isSigned()),
convertCmpKindToICmpPredicate(op.getKind(), shouldUseSigned),
adaptor.getLhs(), adaptor.getRhs());
} else if (mlir::isa<cir::FPTypeInterface>(elementType)) {
bitResult = rewriter.create<mlir::LLVM::FCmpOp>(
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13 changes: 13 additions & 0 deletions clang/test/CIR/Lowering/vec-cmp.cir
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@

!s16i = !cir.int<s, 16>
!u16i = !cir.int<u, 16>
!u8i = !cir.int<u, 8>

cir.func @vec_cmp(%0: !cir.vector<!s16i x 16>, %1: !cir.vector<!s16i x 16>) -> () {
%2 = cir.vec.cmp(lt, %0, %1) : !cir.vector<!s16i x 16>, !cir.vector<!cir.int<u, 1> x 16>
Expand All @@ -14,3 +15,15 @@ cir.func @vec_cmp(%0: !cir.vector<!s16i x 16>, %1: !cir.vector<!s16i x 16>) -> (
// MLIR-NEXT: %{{[0-9]+}} = llvm.icmp "slt" %arg0, %arg1 : vector<16xi16>
// MLIR-NEXT: %{{[0-9]+}} = llvm.bitcast %{{[0-9]+}} : vector<16xi1> to i16
// MLIR-NEXT: llvm.return

cir.func @vec_cmp_zero(%0: !cir.vector<!u8i x 16>) -> () {
%1 = cir.const #cir.zero : !cir.vector<!u8i x 16>
%2 = cir.vec.cmp(lt, %0, %1) : !cir.vector<!u8i x 16>, !cir.vector<!cir.int<u, 1> x 16>
%3 = cir.cast(bitcast, %2 : !cir.vector<!cir.int<u, 1> x 16>), !cir.int<u, 16>

cir.return
}

// MLIR: llvm.func @vec_cmp_zero
// MLIR: %{{[0-9]+}} = llvm.icmp "slt" %arg0, %{{[0-9]+}} : vector<16xi8>
// MLIR-NEXT: %{{[0-9]+}} = llvm.bitcast %{{[0-9]+}} : vector<16xi1> to i16
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