All pull requests

Pull requests

• [circt-lec][circt-bmc] Run canonicalization and CSE in nested PMs

  #11558·fzi-hielscher opened Nov 12, 2026Contributor·

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• [HW] Fix IMDCE crash on blocks nested in side-effecting ops

  #11557·rslawson opened Nov 12, 2026·

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  1

• [FIRRTL] Add a pass that names modules by a hash of their contents

  #11555·oharboe opened Nov 12, 2026·

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  2

• [CAPI][Sim] Expose DPI function types

  #11554·Clo91eaf opened Nov 12, 2026Contributor·

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  1

• [MooreToCore] Support dynamic extract_ref on single field packed struct

  run-circt-tests
  #11553·VecoMr opened Nov 12, 2026Member·

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  2

• [FIRRTL] Fix getIntOnesAttr for widths over 64 bits

  #11551·0z5a opened Nov 11, 2026·

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• [HW] Support StructExplodeOp in HWAggregateToComb

  #11549·AlviseDeFaveri opened Nov 11, 2026Contributor·

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  3

• [ImportVerilog] Support $past(expr, number_of_tick) and error explicitly on unhandled sampled-value arities

  run-circt-tests
  #11548·AlviseDeFaveri opened Nov 11, 2026Contributor·

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  12

• [LLHD] Hoist projections during canonicalization

  run-circt-tests
  #11547·AlviseDeFaveri opened Nov 11, 2026Contributor·

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  5

• [LLHD] UnrollLoops: run on processes as well

  run-circt-tests
  #11546·AlviseDeFaveri opened Nov 11, 2026Contributor·

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  7

• [LLHD] Add ProbeLikeOp Interface

  #11544·TaoBi22 opened Nov 11, 2026Contributor·2/2·

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• [LLHD] Rename probe_net operand to $net

  #11543·TaoBi22 opened Nov 11, 2026Contributor·1/2·

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• [LLHD][HoistSignals] Add net support

  #11542·TaoBi22 opened Nov 11, 2026Contributor·

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• [LLHD] Accept single whole-signal drives on unions in CombineDrives

  #11541·jmolloy opened Nov 11, 2026Contributor·

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• [OM] list.contains object/ref eval support

  #11538·seldridge opened Nov 11, 2026Member·2/2·

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• [FIRRTL] Allow class, anyref in list.contains

  #11537·seldridge opened Nov 11, 2026Member·1/2·

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  2

• [ExportVerilog] Migrate !hw.inout to SV handles

  #11534·okekayode opened Nov 10, 2026Contributor·

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• [DebugInfo] Compare emitted types by value in HGLDD array emission

  #11532·dtzSiFive opened Nov 10, 2026Contributor·

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• [ImportVerilog] Support dual-edge edge-sensitive sequential user-defined primitives (UDPs). (3/3)

  run-circt-tests
  #11531·qiaozhang-pr opened Nov 10, 2026Contributor·

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  2

• [ImportVerilog] Support single-edge edge-sensitive sequential user-defined primitives (UDPs). (2/3)

  run-circt-tests
  #11515·qiaozhang-pr opened Nov 7, 2026Contributor·

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  2

• [Arc] Add basic LLHD signal, probe, and assign support

  ArcLLHD
  #11507·fabianschuiki opened Nov 7, 2026Contributor·

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  1

• Preserve SystemVerilog instance attributes and elaborated parameters.

  #11506·jpienaar opened Nov 6, 2026Member·

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• [Moore] Allow union_extract_ref on nets

  #11501·TaoBi22 opened Nov 6, 2026Contributor·2/2·

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• [Moore] Support struct_extract_ref on nets

  #11500·TaoBi22 opened Nov 6, 2026Contributor·1/2·

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• [SeqToSV] Don't reuse a cached sv.if whose condition was replaced

  #11499·DecodeTheEncoded opened Nov 6, 2026·

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