NS Interrupt notification over async notif

Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml

@@ -40,6 +40,16 @@ properties:
       HVC #0, register assignments
       register assignments are specified in drivers/tee/optee/optee_smc.h
 
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 1
+    description: |
+      OP-TEE exposes irq for irp chip controllers from OP-TEE world. Each
+      irq is assigned a single line number identifier used as first argument.
+      Line number identifiers and their meaning shall be found in the OP-TEE
+      firmware platform documentation.
+
 required:
   - compatible
   - method
@@ -64,3 +74,31 @@ examples:
             method = "hvc";
         };
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    firmware  {
+        optee: optee {
+            compatible = "linaro,optee-tz";
+            method = "smc";
+            interrupt-parent = <&gic>;
+            interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
+            interrupt-controller;
+            #interrupt-cells = <1>;
+        };
+
+        scmi {
+            compatible = "linaro,scmi-optee";
+            linaro,optee-channel-id = <0>;
+            shmem = <&scmi_shm_tx>, <&scmi_shm_rx>;
+            interrupts-extended = <&optee 5>;
+            interrupt-names = "a2p";
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            scmi_cpu_dvfs: protocol@13 {
+                reg = <0x13>;
+                #clock-cells = <1>;
+            };
+        };
+    };

arch/arm/boot/dts/stm32mp151.dtsi

@@ -35,6 +35,14 @@
 		method = "smc";
 	};
 
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+			status = "disabled";
+		};
+	};
+
 	intc: interrupt-controller@a0021000 {
 		compatible = "arm,cortex-a7-gic";
 		#interrupt-cells = <3>;

arch/arm/boot/dts/stm32mp157c-dk2.dts

@@ -16,6 +16,13 @@
 	model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
 	compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
 
+	reserved-memory {
+		optee_memory: optee@0xde000000 {
+			reg = <0xde000000 0x02000000>;
+			no-map;
+		};
+	};
+
 	aliases {
 		ethernet0 = &ethernet0;
 		serial0 = &uart4;
@@ -99,3 +106,7 @@
 	pinctrl-2 = <&usart2_idle_pins_c>;
 	status = "disabled";
 };
+
+&optee {
+	status = "okay";
+};

arch/arm/boot/dts/stm32mp157c-ed1.dts

@@ -70,6 +70,11 @@
 			reg = <0xe8000000 0x8000000>;
 			no-map;
 		};
+
+		optee_memory: optee@fe000000 {
+			reg = <0xfe000000 0x2000000>;
+			no-map;
+		};
 	};
 
 	aliases {
@@ -320,6 +325,10 @@
 	status = "okay";
 };
 
+&optee {
+	status = "okay";
+};
+
 &pwr_regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;

arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi

@@ -61,6 +61,11 @@
 			reg = <0x38000000 0x10000>;
 			no-map;
 		};
+
+		optee_memory: optee@fe000000 {
+			reg = <0xfe000000 0x2000000>;
+			no-map;
+		};
 	};
 
 	ethernet_vio: vioregulator {
@@ -421,6 +426,10 @@
 	status = "okay";
 };
 
+&optee {
+	status = "okay";
+};
+
 &pwr_regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;

arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi

@@ -60,6 +60,11 @@
 			reg = <0x38000000 0x10000>;
 			no-map;
 		};
+
+		optee_memory: optee@fe000000 {
+			reg = <0xfe000000 0x2000000>;
+			no-map;
+		};
 	};
 };
 
@@ -240,6 +245,10 @@
 	status = "okay";
 };
 
+&optee {
+	status = "okay";
+};
+
 &pwr_regulators {
 	vdd-supply = <&vdd>;
 	vdd_3v3_usbfs-supply = <&vdd_usb>;

arch/arm64/boot/dts/arm/foundation-v8.dtsi

@@ -22,11 +22,14 @@
 
 	aliases {
 		serial0 = &v2m_serial0;
-		serial1 = &v2m_serial1;
 		serial2 = &v2m_serial2;
 		serial3 = &v2m_serial3;
 	};
 
+	ftpm {
+	        compatible = "microsoft,ftpm";
+	};
+
 	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
@@ -68,6 +71,17 @@
 		      <0x00000008 0x80000000 0 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		optee@0x83000000 {
+			reg = <0x00000000 0x83000000 0 0x01000000>;
+			no-map;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -202,14 +216,6 @@
 				clock-names = "uartclk", "apb_pclk";
 			};
 
-			v2m_serial1: serial@a0000 {
-				compatible = "arm,pl011", "arm,primecell";
-				reg = <0x0a0000 0x1000>;
-				interrupts = <6>;
-				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-				clock-names = "uartclk", "apb_pclk";
-			};
-
 			v2m_serial2: serial@b0000 {
 				compatible = "arm,pl011", "arm,primecell";
 				reg = <0x0b0000 0x1000>;
@@ -233,4 +239,12 @@
 			};
 		};
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
 };

arch/arm64/boot/dts/arm/fvp-base-revc.dts

@@ -183,6 +183,11 @@
 			reg = <0x00000000 0x18000000 0 0x00800000>;
 			no-map;
 		};
+
+		optee@83000000 {
+			reg = <0x00000000 0x83000000 0 0x01000000>;
+			no-map;
+		};
 	};
 
 	gic: interrupt-controller@2f000000 {
@@ -317,4 +322,11 @@
 				<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 				<0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
 };

arch/arm64/boot/dts/arm/juno-base.dtsi

@@ -967,6 +967,18 @@
 		      <0x00000008 0x80000000 0x1 0x80000000>;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Shared memory between secure and non-secure world */
+		optee@0xfee00000 {
+			reg = <0x00000000 0xfee00000 0 0x00200000>;
+			no-map;
+		};
+	};
+
 	bus@8000000 {
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 15>;
@@ -994,4 +1006,11 @@
 		interrupt-map-mask = <0 0>;
 		interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
 };

arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts

@@ -6,6 +6,7 @@
  */
 
 /dts-v1/;
+/memreserve/ 0x00000000 0x04080000;
 
 #include <dt-bindings/gpio/gpio.h>
 #include "hi3798cv200.dtsi"
@@ -70,6 +71,13 @@
 		gpio = <&gpio6 7 0>;
 		enable-active-high;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
 };
 
 &ehci {

arch/arm64/boot/dts/mediatek/mt8173-evb.dts

@@ -60,6 +60,13 @@
 		gpio = <&pio 9 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
 };
 
 &mfg_async {

arch/arm64/boot/dts/mediatek/mt8173.dtsi

@@ -526,15 +526,6 @@
 			reg = <0 0x10007000 0 0x100>;
 		};
 
-		timer: timer@10008000 {
-			compatible = "mediatek,mt8173-timer",
-				     "mediatek,mt6577-timer";
-			reg = <0 0x10008000 0 0x1000>;
-			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&infracfg CLK_INFRA_CLK_13M>,
-				 <&topckgen CLK_TOP_RTC_SEL>;
-		};
-
 		pwrap: pwrap@1000d000 {
 			compatible = "mediatek,mt8173-pwrap";
 			reg = <0 0x1000d000 0 0x1000>;

arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi

@@ -167,6 +167,24 @@
 		regulator-min-microvolt = <800000>;
 		regulator-max-microvolt = <1400000>;
 	};
+
+       firmware {
+	       optee {
+		       compatible = "linaro,optee-tz";
+		       method = "smc";
+	       };
+       };
+
+       reserved-memory {
+	       #address-cells = <2>;
+	       #size-cells = <2>;
+	       ranges;
+
+	       optee@30000000 {
+		       reg = <0x0 0x30000000 0x0 0x2400000>;
+		       no-map;
+	       };
+       };
 };
 
 &cpu_l0 {
@@ -765,7 +783,7 @@
 };
 
 &usbdrd_dwc3_0 {
-	status = "okay";
+	status = "disabled";
 	dr_mode = "host";
 };
 

drivers/tee/optee/optee_private.h

@@ -94,11 +94,21 @@ struct optee_supp {
 	struct completion reqs_c;
 };
 
+/*
+ * struct optee_smc - optee smc communication struct
+ * @invoke_fn		handler function to invoke secure monitor
+ * @memremaped_shm	virtual address of memory in shared memory pool
+ * @sec_caps:		secure world capabilities defined by
+ *			OPTEE_SMC_SEC_CAP_* in optee_smc.h
+ * @notif_irq		interrupt used as async notification by OP-TEE or 0
+ * @domain		interrupt domain registered by OP-TEE driver
+ */
 struct optee_smc {
 	optee_invoke_fn *invoke_fn;
 	void *memremaped_shm;
 	u32 sec_caps;
 	unsigned int notif_irq;
+	struct irq_domain *domain;
 };
 
 /**