Chisel RISC-V Vector 1.0 Implementation

Like VexRiscv, but, Harder, Better, Faster, Stronger

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

RISC-V Nox core

TFLite model analyzer & memory optimizer

The book "Performance Analysis and Tuning on Modern CPU"

A Linux-capable RISC-V multicore for and by the world

Instant voice cloning by MIT and MyShell. Audio foundation model.

The OpenPiton Platform

RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC

A C++ simulator and SystemVerilog implementation of the RISC-V R32IM architecture.

Experience macOS just like before

Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7

The Linux Kernel Module Programming Guide (updated for 5.0+ kernels)

A Fast, Low-Overhead On-chip Network

A simple superscalar out-of-order RISC-V microprocessor

Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the…

The multi-core cluster of a PULP system.

SystemC/TLM-2.0 Co-simulation framework

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

FPGA GPU design for DE1-SoC

RISC-V IOMMU Specification

Doom classic port to lightweight RISC‑V

Demo projects for various Kintex FPGA boards

Provides network connectivity to WSL 2 when blocked by VPN

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SDK for Greenwaves Technologies' GAP8 IoT Application Processor