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1 parent 1642542 commit 0d954beCopy full SHA for 0d954be
indent/verilog_systemverilog.vim
@@ -51,7 +51,7 @@ let s:vlog_define = '^\s*`define\>'
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let s:vlog_case = '\<case[zx]\?\>\s*('
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let s:vlog_join = '\<join\(_any\|_none\)\?\>'
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-let s:vlog_block_decl = '\(\<\(while\|if\|foreach\|for\)\>\s*(\)\|\<\(else\|do\)\>\|' . s:vlog_always
+let s:vlog_block_decl = '\(\<\(while\|if\|foreach\|for\|repeat\)\>\s*(\)\|\<\(initial\|forever\|else\|do\)\>\|' . s:vlog_always
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let s:vlog_context_end = '\<end\(package\|function\|class\|module\|group\|generate\|program\|property\|sequence\|clocking\|interface\|task\)\>\|`endif\>'
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