Indent: Implement indentation on standalone blocks

Disable is controlled through g:verilog_disable_indent_lst and its
default was updated to also include `standalone` to mimic original
behavior.
Nonetheless, if this variable is defined in user's .vimrc then it will
need to be updated to recover the previous behavior.

Author: vhda

autoload/verilog_systemverilog.vim

@@ -601,7 +601,8 @@ function verilog_systemverilog#CompleteCommand(lead, command, cursor)
           \ 'method',
           \ 'preproc',
           \ 'conditional',
-          \ 'eos'
+          \ 'eos',
+          \ 'standalone'
           \ ]
     for item in current_values
       call filter(valid_completions, 'v:val !=# item')

doc/verilog_systemverilog.txt

@@ -387,7 +387,7 @@ Example:
                    *b:verilog_disable_indent_lst* *g:verilog_disable_indent_lst*
 b:verilog_disable_indent_lst~
 g:verilog_disable_indent_lst~
-Default: "eos"
+Default: "eos,standalone"
 
     Disables indent for specific Verilog/SystemVerilog contexts.
     The following contexts are supported:
@@ -404,25 +404,26 @@ Default: "eos"
         - `preproc`
         - `conditional`
         - `eos`
+        - `standalone`
 
-Example:
+Examples:
 
 >
     let g:verilog_disable_indent_lst = "module,class,interface"
 <
     Disabling indentation of `conditional` will change the following:
 >
-    // Default indent
-    assign a = cond ? b :
-                      c ;
-    // Disabling 'conditional'
-    assign a = cond ? b :
-               c ;
+        // Default indent
+        assign a = cond ? b :
+                          c ;
+        // Disabling 'conditional'
+        assign a = cond ? b :
+                   c ;
 <
 
     Disabling indentation of `eos` will affect how the closing parentheses of
     modules, functions, tasks, etc. are indented.
-    By default:
+    When enabled:
 >
         module mod(
             input wire a,
@@ -437,6 +438,23 @@ Example:
         );
 <
 
+    Disabling indentation of `standalone` will affect how standalone blocks,
+    like begin..end or {..} are indented.
+    When enabled:
+>
+        if (expr)
+            begin
+                func();
+            end
+<
+    When disabled:
+>
+        if (expr)
+        begin
+            func();
+        end
+<
+
     Note: The commands |:VerilogIndentAdd| and |:VerilogIndentRemove| are
     provided to allow an easier management of this variable.
 

indent/verilog_systemverilog.vim

@@ -357,15 +357,20 @@ function! s:GetContextIndent()
       call verilog_systemverilog#Verbose("'begin'..'end' pair.")
       return indent(l:lnum)
     elseif l:oneline_mode == 1 && l:line =~ s:vlog_block_decl && l:line !~ '\<begin\>.*\<end\>'
+      if index(s:verilog_disable_indent, 'standalone') < 0
+        let l:standalone = s:offset
+      else
+        let l:standalone = 0
+      endif
       if s:curr_line =~ '^\s*\<begin\>'
         call verilog_systemverilog#Verbose("Standalone 'begin' after block declaration.")
-        return indent(l:lnum)
+        return indent(l:lnum) + l:standalone
       elseif s:curr_line =~ '^\s*{\s*$' && l:cbracket_level == 0
         call verilog_systemverilog#Verbose("Standalone '{' after block declaration.")
-        return indent(l:lnum)
+        return indent(l:lnum) + l:standalone
       elseif s:curr_line =~ '^\s*(\s*$' && l:bracket_level == 0
         call verilog_systemverilog#Verbose("Standalone '(' after block declaration.")
-        return indent(l:lnum)
+        return indent(l:lnum) + l:standalone
       else
         call verilog_systemverilog#Verbose("Indenting a single line block.")
         return indent(l:lnum) + s:offset + l:open_offset

plugin/verilog_systemverilog.vim

@@ -1,5 +1,5 @@
 " Global plugin settings
-let g:verilog_disable_indent_lst="eos"
+let g:verilog_disable_indent_lst="eos,standalone"
 
 " Command definitions
 command! -nargs=* VerilogErrorFormat call verilog_systemverilog#VerilogErrorFormat(<f-args>)

test/run_test.vim

@@ -52,7 +52,7 @@ endfunction
 " Syntax indent test
 "-----------------------------------------------------------------------
 function! RunTestIndent()
-    let g:verilog_disable_indent_lst = "module,eos"
+    let g:verilog_disable_indent_lst = "module,eos,standalone"
     let test_result=0
 
     " Open syntax indent test file