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Add more ConditionVisitor cases (and fix minor bug) #2

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19 changes: 17 additions & 2 deletions decompiler/decompiler/condition_visitor.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

from binaryninja import (Variable, VariableSourceType)

from z3 import (BitVec, And, Or, Not, Solver, simplify, Extract, UGT, ULE, Array, BitVecSort, Concat, Bool)
from z3 import (BitVec, And, Or, Not, Solver, simplify, Extract, UGT, ULE, UGE, ULT, Array, BitVecSort, Concat, Bool)

def make_variable(var: Variable):
if var.name == '':
Expand Down Expand Up @@ -45,6 +45,11 @@ def visit_MLIL_CMP_SGT(self, expr):

return left > right

def visit_MLIL_CMP_SLT(self, expr):
left, right = self.visit_both_sides(expr)

return left < right

def visit_MLIL_CMP_SGE(self, expr):
left, right = self.visit_both_sides(expr)

Expand All @@ -60,6 +65,16 @@ def visit_MLIL_CMP_ULE(self, expr):

return ULE(left, right)

def visit_MLIL_CMP_UGE(self, expr):
left, right = self.visit_both_sides(expr)

return UGE(left, right)

def visit_MLIL_CMP_ULT(self, expr):
left, right = self.visit_both_sides(expr)

return ULT(left, right)

def visit_MLIL_LOAD(self, expr):
src = self.visit(expr.src)
return make_load(src, expr.size)
Expand Down Expand Up @@ -102,4 +117,4 @@ def visit_MLIL_LSL(self, expr):
def visit_both_sides(self, expr):
return self.visit(expr.left), self.visit(expr.right)

visit_MLIL_CONST_PTR = visit_MLIL_CONST
visit_MLIL_CONST_PTR = visit_MLIL_CONST
2 changes: 1 addition & 1 deletion decompiler/decompiler/linear_mlil.py
Original file line number Diff line number Diff line change
Expand Up @@ -128,7 +128,7 @@ def generateLines(self):
to_visit = [
(n, 0)
for header, n in sorted(
ast._regions.items(), key=cmp_to_key(lambda i, j: 1 if ast.reaching_conditions.get((i[0], j[0])) is None else 1 if i.start > j.start else -1), reverse=True
ast._regions.items(), key=cmp_to_key(lambda i, j: 1 if ast.reaching_conditions.get((i[0], j[0])) is None else 1 if i[0].start > j[0].start else -1), reverse=True
)
]

Expand Down