Start of implementation for NES memory bus #60
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Add a basic APU/PPU and the sketch out basic bus arch. Realized need real RDY support so backtrack a bit and do that. Also update documentatio in cpu.rs so the various traits/macros make sense without a complete reread each time. New tests for RDY pulled out of init
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Bumps [syn](https://github.com/dtolnay/syn) from 2.0.39 to 2.0.41. - [Release notes](https://github.com/dtolnay/syn/releases) - [Commits](dtolnay/syn@2.0.39...2.0.41) --- updated-dependencies: - dependency-name: syn dependency-type: direct:production update-type: version-update:semver-patch ... Signed-off-by: dependabot[bot] <[email protected]> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
* load_register should take a Wrapping if that's how we return regs too. Consistency Investigate op_addr/op_val and it makes the code way messier in the end. In the few places we add just make sure we do it with Wrapping. * Very large update: Added 2 more CPUs: Rockwell 65C02 - Doesn't have STP/WAI but otherwise same as WDC 65SC02 - Doesn't have BBR/BBS/RMB/SMB (replace with various NOPs). In all the CMOE cases there's still disagreement on the bus cycles in some places. Opened one issue for one (BBR/BBS). The rest I just kept notes on for now. Everything passes if we ignore the ones from above so works for what I need. Found a few actual bugs in the end.
Plus MSRV for egui and fixes for that update. New clippy as well.
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Add a basic APU/PPU and the sketch out basic bus arch.
Realized need real RDY support so backtrack a bit and do that.
Also update documentatio in cpu.rs so the various traits/macros make sense without a complete reread each time.
New tests for RDY pulled out of init