-Hardware-Accelerator-Software-implementation-of-MobileNets

Implemented MobileNets neural architecture in PyTorch. Designed a hardware accelerator for MobileNets in System Verilog using Vivado HLx suite and tested on MiniZed development board.

This repository contains:

1. Hardware_code folder containing all system verilog files for design and C code for Board It contains testbench and sample data for simulation purpose. C_code contains C files and .H files for testing purpose
2. MobileNets_Pytorch Pytorch implementation of Mobilenets
3. Output_generation_code contains code from which we are generating out input and weights Generate_output_from_input folder contains code to generate data for available input data Generate_random_output contains code from which generate random data for first layer
4. ESE_587_report: Project Report
5. MobileNets.ppt: Project Presentation
6. Link to project archive: https://drive.google.com/file/d/1o8TvHCNvdG9nNyAU315eGHqeIapta_w7/view?usp=sharing