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Refator UT and improve code coverage#2057

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lvliang-intel wants to merge 20 commits into
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lvl/ut_coverage
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Refator UT and improve code coverage#2057
lvliang-intel wants to merge 20 commits into
mainfrom
lvl/ut_coverage

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Description

Refator UT and improve code coverage.
Motivations:
1 Reduce PR CI time: heavy suites (INC, LLMC, vLLM, SGLang integration, full-model e2e) were previously running on every PR. Moving them to nightly/weekly pipelines cuts PR latency materially.
2 Increase code coverage: the new unit tests target low-coverage modules.

Type of Change

Refactor

Related Issues

#2012
#1792

Checklist Before Submitting

  • My code has been tested locally.
  • Documentation has been updated as needed.
  • New or updated tests are included where applicable.
  • The CUDA CI has passed. You can trigger it by commenting /azp run Unit-Test-CUDA-AutoRound.

XuehaoSun and others added 20 commits July 2, 2026 09:37
Signed-off-by: Sun, Xuehao <xuehao.sun@intel.com>
Signed-off-by: lvliang-intel <liang1.lv@intel.com>
…t_coverage

Signed-off-by: lvliang-intel <liang1.lv@intel.com>
Signed-off-by: lvliang-intel <liang1.lv@intel.com>
…t_coverage

Signed-off-by: lvliang-intel <liang1.lv@intel.com>
…t_coverage

Signed-off-by: lvliang-intel <liang1.lv@intel.com>
Signed-off-by: lvliang-intel <liang1.lv@intel.com>
Signed-off-by: lvliang-intel <liang1.lv@intel.com>
Signed-off-by: lvliang-intel <liang1.lv@intel.com>
…t_coverage

Signed-off-by: lvliang-intel <liang1.lv@intel.com>
Signed-off-by: lvliang-intel <liang1.lv@intel.com>
Signed-off-by: lvliang-intel <liang1.lv@intel.com>
…into lvl/ut_coverage

Signed-off-by: lvliang-intel <liang1.lv@intel.com>
…into lvl/ut_coverage

Signed-off-by: lvliang-intel <liang1.lv@intel.com>
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2 participants