update video timing

CMakeLists.txt

@@ -23,7 +23,7 @@ if (HDZ_BOXPRO)
 	file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/mkapp/app/platform "HDZBOXPRO")
 endif()
 
-option(HDZ_GOGGLE "Target Goggles2" OFF)
+option(HDZ_GOGGLE2 "Target Goggles2" OFF)
 if (HDZ_GOGGLE2)
 	set(COMMON_COMPILER_FLAGS "${COMMON_COMPILER_FLAGS} -DHDZGOGGLE2=1")
 	file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/mkapp/app/platform "HDZGOGGLE2")

mkapp/hal/goggle2/version

@@ -1 +1 @@
-77-184
+77 - 191

src/core/app_state.c

@@ -77,10 +77,6 @@ void app_exit_menu() {
 }
 
 void app_switch_to_analog(bool is_av_in) {
-#ifdef HDZGOGGLE2
-    system_exec("aww 0x0300b084 0x0001555");
-#endif
-
     dvr_update_vi_conf(VR_720P50);
     osd_fhd(0);
     osd_show(true);
@@ -110,10 +106,17 @@ void app_switch_to_analog(bool is_av_in) {
 }
 
 void app_switch_to_hdmi_in() {
+#if defined HDZBOXPRO
+    // Restore image settings from av module
+    screen.brightness(g_setting.image.oled);
+    Set_Contrast(g_setting.image.contrast);
+#endif
+
 #if defined HDZGOGGLE2
     system_exec("aww 0x0300b084 0x0001555");
 #endif
-    rtc6715.init(0, 0);
+
+  rtc6715.init(0, 0);
 
     Source_HDMI_in();
     IT66121_close();
@@ -149,6 +152,12 @@ void app_switch_to_hdmi_in() {
 void app_switch_to_hdzero(bool is_default) {
     int ch;
 
+#if defined HDZBOXPRO
+    // Restore image settings from av module
+    screen.brightness(g_setting.image.oled);
+    Set_Contrast(g_setting.image.contrast);
+#endif
+
 #if defined HDZGOGGLE2
     system_exec("aww 0x0300b084 0x0001555");
 #endif

src/core/dvr.c

@@ -159,6 +159,7 @@ void dvr_update_vi_conf(video_resolution_t fmt) {
 #endif
     }
     pthread_mutex_unlock(&dvr_mutex);
+    sync();
 
     LOGI("update_record_vi_conf: fmt=%d", fmt);
 }

src/core/msp_displayport.c

@@ -250,6 +250,13 @@ void camTypeDetect(uint8_t rData) {
         load_fc_osd_font(cur_cam == VR_1080P30);
 #elif defined(HDZBOXPRO)
         load_fc_osd_font(0);
+#endif
+    } else if (cur_cam == VR_1080P24 || last_cam == VR_1080P24) {
+        // LOGI("Cam_mode changed:%d", cur_cam);
+#if defined(HDZGOGGLE) || defined(HDZGOGGLE2)
+        load_fc_osd_font(cur_cam == VR_1080P24);
+#elif defined(HDZBOXPRO)
+        load_fc_osd_font(0);
 #endif
     }
 }
@@ -267,7 +274,7 @@ void fcTypeDetect(uint8_t *rData) {
 
         // LOGI("fc_variant changed:%s", fc_variant_rcv);
 #if defined(HDZGOGGLE) || defined(HDZGOGGLE2)
-        load_fc_osd_font(cur_cam == VR_1080P30);
+        load_fc_osd_font(cur_cam == VR_1080P30 || cur_cam == VR_1080P24);
 #elif defined(HDZBOXPRO)
         load_fc_osd_font(0);
 #endif

src/core/self_test.c

@@ -17,6 +17,7 @@
 #include "driver/it66121.h"
 #include "driver/tp2825.h"
 #include "ui/page_common.h"
+#include "util/system.h"
 
 #define UART_WAIT (100 * 1000)
 
@@ -25,6 +26,13 @@ void self_test() {
     uint32_t dat0, dat1;
     char *msg[2] = {"[Error]", "[Pass] "};
 
+#ifdef HDZGOGGLE2
+    system_exec("dispw -s vdpo 1080p50");
+    system_exec("aww 0x0300b340 0x00000008");
+    system_exec("aww 0x0300b084 0x00002aaa"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
+
+#endif
+
     if (!g_setting.storage.selftest)
         return;
 

src/driver/hardware-goggle2.c

@@ -39,19 +39,19 @@ int fhd_req = 0;
 pthread_mutex_t hardware_mutex;
 
 uint32_t vclk_phase_default[VIDEO_SOURCE_NUM] = {
-    // 0x8d,  0x8e,  0x14,  hdmi_out
-    0x00000006, // VIDEO_SOURCE_VERSION
-    0x10840000, // VIDEO_SOURCE_MENU_UI
-    0x10840000, // VIDEO_SOURCE_HDZERO_IN_720P60_50
-    0x10840000, // VIDEO_SOURCE_HDZERO_IN_720P90
-    0x10840000, // VIDEO_SOURCE_HDZERO_IN_1080P30
-    0x10840000, // VIDEO_SOURCE_AV_IN
-    0x10040000, // VIDEO_SOURCE_HDMI_IN_1080P50
-    0x10040000, // VIDEO_SOURCE_HDMI_IN_1080P60
-    0x10040000, // VIDEO_SOURCE_HDMI_IN_1080POTHER
-    0x00040000, // VIDEO_SOURCE_HDMI_IN_720P50
-    0x00040000, // VIDEO_SOURCE_HDMI_IN_720P60
-    0x10040000, // VIDEO_SOURCE_HDMI_IN_720P100
+    // 0x??,  0x8e,  0x??, 0x??
+    0x0000000c, // VIDEO_SOURCE_VERSION
+    0x00200000, // VIDEO_SOURCE_MENU_UI
+    0x00010000, // VIDEO_SOURCE_HDZERO_IN_720P60_50
+    0x00200000, // VIDEO_SOURCE_HDZERO_IN_720P90
+    0x00000000, // VIDEO_SOURCE_HDZERO_IN_1080P30
+    0x00010000, // VIDEO_SOURCE_AV_IN
+    0x00200000, // VIDEO_SOURCE_HDMI_IN_1080P50
+    0x00200000, // VIDEO_SOURCE_HDMI_IN_1080P60
+    0x00000000, // VIDEO_SOURCE_HDMI_IN_1080POTHER
+    0x00000000, // VIDEO_SOURCE_HDMI_IN_720P50
+    0x00000000, // VIDEO_SOURCE_HDMI_IN_720P60
+    0x00200000, // VIDEO_SOURCE_HDMI_IN_720P100
     0x00000000, // VIDEO_SOURCE_TP2825_EX
 };
 
@@ -64,15 +64,15 @@ bit[5:4] hdmi out
 bit[6]   oled
 */
 uint32_t pclk_phase_default[VIDEO_SOURCE_NUM] = {
-    0x00000001,
-    0x00000004, // VIDEO_SOURCE_MENU_UI
+    0x00000003,
+    0x00000000, // VIDEO_SOURCE_MENU_UI
     0x00000000, // VIDEO_SOURCE_HDZERO_IN_720P60_50
     0x00000000, // VIDEO_SOURCE_HDZERO_IN_720P90
     0x00000000, // VIDEO_SOURCE_HDZERO_IN_1080P30
     0x00000000, // VIDEO_SOURCE_AV_IN
-    0x00000000, // VIDEO_SOURCE_HDMI_IN_1080P50
-    0x00000000, // VIDEO_SOURCE_HDMI_IN_1080P60
-    0x00000000, // VIDEO_SOURCE_HDMI_IN_1080POTHER
+    0x00000001, // VIDEO_SOURCE_HDMI_IN_1080P50
+    0x00000001, // VIDEO_SOURCE_HDMI_IN_1080P60
+    0x00000001, // VIDEO_SOURCE_HDMI_IN_1080POTHER
     0x00000000, // VIDEO_SOURCE_HDMI_IN_720P50
     0x00000000, // VIDEO_SOURCE_HDMI_IN_720P60
     0x00000000, // VIDEO_SOURCE_HDMI_IN_720P100
@@ -262,33 +262,11 @@ uint8_t vclk_phase_inv_read_file(char *file_path) {
 
             vclk_phase[mode] = vclk_phase_default[mode];
 
-            if (mode == VIDEO_SOURCE_TP2825_EX) {
-                vclk_phase[mode] = value;
-            } else {
-                if ((value >> 0) & 1) // 14[0]
-                    vclk_phase[mode] ^= (1 << 8);
-
-                if ((value >> 1) & 1) // 8e[7]
-                    vclk_phase[mode] ^= (1 << 23);
+            if ((value >> 0) & 1) // 0x8e[0]
+                vclk_phase[mode] ^= (1 << 16);
 
-                if ((value >> 2) & 1) // 8d[2]
-                    vclk_phase[mode] ^= (1 << 26);
-
-                if ((value >> 3) & 1) // hdmi out_0
-                    vclk_phase[mode] ^= (1 << 0);
-
-                if ((value >> 4) & 1) // hdmi out_1
-                    vclk_phase[mode] ^= (1 << 1);
-
-                if ((value >> 5) & 1) // 8d[4]
-                    vclk_phase[mode] ^= (1 << 28);
-
-                if ((value >> 6) & 1) // 8d[3]
-                    vclk_phase[mode] ^= (1 << 27);
-
-                if ((value >> 7) & 1) // 8e[2]
-                    vclk_phase[mode] ^= (1 << 18);
-            }
+            if ((value >> 1) & 1) // 0x8e[5]
+                vclk_phase[mode] ^= (1 << 21);
 
             LOGI("%s 0x%02x, ori:0x%08x new:0x%08x", type_str, value, vclk_phase_default[mode], vclk_phase[mode]);
         }
@@ -358,14 +336,14 @@ void vclk_phase_load_system() {
 
     if (vclk_phase_read_file("/etc/vclk_phase.cfg")) {
         // if no .cfg file, write it.
-        // vclk_phase_write_file("/etc/vclk_phase.cfg", vclk_phase_default);
+        vclk_phase_write_file("/etc/vclk_phase.cfg", vclk_phase_default);
 
         for (i = 0; i < VIDEO_SOURCE_NUM; i++) {
             vclk_phase[i] = vclk_phase_default[i];
         }
     } else if (vclk_phase_load[VIDEO_SOURCE_VERSION] != 0xffffffff && vclk_phase_load[VIDEO_SOURCE_VERSION] != vclk_phase_default[VIDEO_SOURCE_VERSION]) {
         // newer .cfg file version
-        // vclk_phase_write_file("/etc/vclk_phase.cfg", vclk_phase_default);
+        vclk_phase_write_file("/etc/vclk_phase.cfg", vclk_phase_default);
 
         for (i = 0; i < VIDEO_SOURCE_NUM; i++) {
             vclk_phase[i] = vclk_phase_default[i];
@@ -411,7 +389,7 @@ void vclk_phase_inv_load_sdcard() {
         return;
     }
 
-    // vclk_phase_write_file("/etc/vclk_phase.cfg", vclk_phase);
+    vclk_phase_write_file("/etc/vclk_phase.cfg", vclk_phase);
 
     system_exec("rm /mnt/extsd/vclk_phase_inv.txt");
 }
@@ -441,7 +419,7 @@ void pclk_phase_dump() {
 
 void vclk_phase_init() {
     vclk_phase_load_system();
-    // vclk_phase_inv_load_sdcard();
+    vclk_phase_inv_load_sdcard();
     vclk_phase_dump();
 }
 
@@ -451,20 +429,7 @@ void pclk_phase_init() {
 }
 
 void vclk_phase_set(video_source_t source, uint8_t reg_8d_sel) {
-    if (reg_8d_sel)
-        I2C_Write(ADDR_FPGA, 0x8d, (((vclk_phase[source] >> 24) & 0xff) ^ (1 << 4)));
-    else
-        I2C_Write(ADDR_FPGA, 0x8d, (vclk_phase[source] >> 24) & 0xff);
-
-    if (source == VIDEO_SOURCE_HDZERO_IN_720P60_50 || source == VIDEO_SOURCE_HDZERO_IN_720P90) {
-        I2C_Write(ADDR_FPGA, 0x8e, 0x01);
-    } else {
-        I2C_Write(ADDR_FPGA, 0x8e, (vclk_phase[source] >> 16) & 0xff);
-    }
-
-    I2C_Write(ADDR_AL, 0x14, (vclk_phase[source] >> 8) & 0xff);
-
-    IT66121_set_phase(vclk_phase[source] & 3, 0);
+    I2C_Write(ADDR_FPGA, 0x8e, (vclk_phase[source] >> 16) & 0xff);
 }
 
 /*
@@ -515,6 +480,7 @@ void csic_pclk_invert_set(uint8_t is_invert) {
 }
 
 void pclk_phase_set(video_source_t source) {
+    LOGI("video_source:%d", source);
     LOGI("pclk_phase_set %d", pclk_phase[source]);
     // bit[0] hdmi in
     if (source == VIDEO_SOURCE_HDMI_IN_1080P50 || source == VIDEO_SOURCE_HDMI_IN_1080P60 || source == VIDEO_SOURCE_HDMI_IN_1080POTHER) {
@@ -589,7 +555,7 @@ void Display_UI_init() {
     I2C_Write(ADDR_FPGA, 0x84, 0x11);
 
     screen.vtmg(0);
-    system_exec("aww 0x0300b084 0x00002aaa"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
+    system_exec("aww 0x0300b084 0x00003fff"); // Set vdpo clock driver strength to level 2. Refer datasheet 12.7.5.11
     I2C_Write(ADDR_FPGA, 0xa7, 0x00);
     system_exec("aww 0x06542018 0x00000044"); // disable horizontal chroma FIR filter.
 }
@@ -782,16 +748,18 @@ int HDZERO_detect() // return = 1: vtmg to V536 changed
                 break;
             case VR_1080P30:
                 Display_1080P30_t(CAM_MODE);
-
+                break;
+            case VR_1080P24:
+                Display_1080P24_t(CAM_MODE);
                 break;
             default:
                 LOGW("cam_mode =%d not suppored!!\n ", CAM_MODE);
                 break;
             }
 
-            if (CAM_MODE == VR_1080P30)
+            if (CAM_MODE == VR_1080P30 || CAM_MODE == VR_1080P24)
                 fhd_req = 1;
-            else if (cam_mode_last == VR_1080P30)
+            else if (cam_mode_last == VR_1080P30 || cam_mode_last == VR_1080P24)
                 fhd_req = -1;
             dvr_update_vi_conf(CAM_MODE);
             system_script(REC_STOP_LIVE);
@@ -1226,24 +1194,23 @@ int Get_VideoLatancy_status() // ret: 0=unlocked, 1=locked
 
 int Get_HAN_status() // ret: 0=error; 1=ok
 {
-    uint8_t rdat;
-
-    system_exec("aww 0x0300b340 0x00000008");
+    uint8_t r18 = 0;
+    uint8_t r19 = 0;
 
     I2C_Write(ADDR_FPGA, 0x81, 0x01);
+    sleep(1);
 
-    usleep(10000);
-
-    rdat = I2C_Read(ADDR_FPGA, 0x18);
+    r18 = I2C_Read(ADDR_FPGA, 0x18);
+    r19 = I2C_Read(ADDR_FPGA, 0x19);
 
-    if (rdat >= 0xE4 && rdat <= 0xE7)
-        rdat = 1;
+    if (r19 == 0x1C && r18 >= 0xF0 && r18 <= 0xF6)
+        r19 = 1;
     else
-        rdat = 0;
+        r19 = 0;
 
     I2C_Write(ADDR_FPGA, 0x81, 0x00);
 
-    return rdat;
+    return r19;
 }
 
 #endif

src/driver/it66021.c

@@ -372,7 +372,7 @@ void IT66021_edid() {
 void IT66021_Set_Pclk(int inv, int dly) {
     IT66021_Mask_WR(0, 0x0f, 0x03, 0x00);
     if (inv)
-        I2C_L_Write(ADDR_IT66021, 0x50, 0xA0 + dly);
+        I2C_L_Write(ADDR_IT66021, 0x50, 0xB2);
     else
-        I2C_L_Write(ADDR_IT66021, 0x50, 0xB0 + dly);
+        I2C_L_Write(ADDR_IT66021, 0x50, 0xA1);
 }