Vitis Accelerator IP Flow #1134

steltze · 2024-11-20T13:28:28Z

Vitis Accelerator based on the IP Flow for Zynq devices (in contrast to #991 ), similar to the Vivado Accelerator.

Inherits from the Vitis backend
Generates the AXI wrapper around the typical hls4ml IP and the test bench
Automatically creates a Vivado project with the block design, imports the IP, and generates the bitstream

Tested on

Vivado and Vitis HLS v2023.2
ZCU102 (pynq v3 ported on an ubuntu image) and PYNQ-Z2 (official v3.0.1 image) using AXI-Stream and io_stream and io_parallel with a small MLP
Tested the Vivado/VivadoAccelerator backends as well to check that nothing broke

To dos:

Integrate AXI-Master interface as an option
Include tar generation with the bitstream, design files for pynq and the python driver for pynq
Include FIFO Depth Optimization as a backend pass (similar to FIFO depth optimizer for Vitis backend #1037 )

Type of change

New feature (non-breaking change which adds functionality)

Tests

Pending unit tests

Test Configuration:

Checklist

I have read the guidelines for contributing.
I have commented my code, particularly in hard-to-understand areas.
I have made corresponding changes to the documentation.
My changes generate no new warnings. Some warnings occur due to ap_axi_sdata.h
I have installed and run pre-commit on the files I edited or added.
I have added tests that prove my fix is effective or that my feature works.

…rning#956) * Stage initial set of changes for the Catapult backend * applied some changes for issues reported by pre-commit. But pre-commit still reorders backends/__init__.py incorrectly * final changes for clean pre-commit * minor edits * Checkin * Add file * pre-commit format * add in nnet_utils files * format changes for pre-commit * run flows by netlist type * update design pragmas on some blocks. cleaned up TCL script * move AC submodules under hls4ml/templates/catapult * merged in latest changes from mainline * remove bad submodules * recreate AC submodules in hls4ml/templates/catapult * pre-commit fixes * pre-commit fixes * turn on Catapult backend testing * removed io_parallel testing for Catapult backend * add Catapult * added Catapult * added Catapult * added Catapult to some pytests * Added concept of ProjectDir to distinguish the project directory of the HLS tool from the ProjectName which is used for the cpp file and top function name * better handling of c++ testbench data files. enhanced directory naming. * fix syntax * workaround from Giuseppe * Add concept of ProjectDir for Catapult which is different from ProjectName that gets used for the top function name and the cpp files * add new file from Giuseppe * improvements to project management, reporting and testbench * include new file in generation of parameters.h * add hard_tanh for io_parallel. formatting * Full path to the header nnet_helpers.h is necessary in the include (check if this is not an issue with recent versions of Catapult) * Avoid ceiling function from the math library: ceil(n/d) ---> (n+d-1)/n * These are mostly workarounds for the BUP synyhesis of a testing model (should these changes make in something more general?) * revert format back to what clang-format currently enforces * simplification from Giuesspe * Fixes for bottom-up handling of libraries * pre-commit format fixes * fix loops * consolidate prj scripts * cleanup pragmas * switch from using ssh to https for submodules * fix include path for non-catapult install * update pytest environment * CL 1100381 * CL 1098112 * roll in latest changes. turn off Catapult variants of test_binary_cnn and test_cnn_mnist_qkeras for now * fix test failure * disable Catapult test for pytorch until it is supported * disable Catapult for pytorch tests * Simpler submodule initialization for CI --------- Co-authored-by: David Burnette <[email protected]> Co-authored-by: Giuseppe Di Guglielmo <[email protected]> Co-authored-by: Jovan Mitrevski <[email protected]> Co-authored-by: Vladimir Loncar <[email protected]>

updates: - [github.com/psf/black: 24.3.0 → 24.4.0](psf/black@24.3.0...24.4.0)

hls4ml/templates/vitis/nnet_utils/nnet_sepconv1d_stream.h

hls4ml/templates/vitis/nnet_utils/nnet_sepconv2d_stream.h

nghielme · 2025-02-22T23:20:59Z

hls4ml/backends/vitis_accelerator_ip_flow/vitis_accelerator_ip_flow_backend.py

+
+class VitisAcceleratorIPFlowBackend(VitisBackend):
+    def __init__(self):
+        super(VivadoBackend, self).__init__(name='VitisAcceleratorIPFlow')


Why calling super(VivadoBackend, self) and not super(VitisBackend, self)?

it does not work cause VitisBackend already sets the name. I could find a workaround

I think this is a result of the strange inheritance structure that we have. We will try to rationalize it in the future, so hopefully this can be updated then. But for now, given the mess our inheritance structure is, I think whatever works is fine.

hls4ml/backends/vitis_accelerator_ip_flow/vitis_accelerator_ip_flow_backend.py

test/pytest/test_optimization/test_fifo_depth.py

hls4ml/templates/vitis_accelerator_ip_flow/build_lib.sh

nghielme · 2025-03-03T17:27:41Z

hls4ml/backends/vitis_accelerator_ip_flow/passes/fifo_depth_optimization.py

I'd keep FIFO depth optimisation for VitisAccelerator as a separate PR

…ration

DivineMK · 2025-03-28T13:54:20Z

hls4ml/templates/vitis_accelerator_ip_flow/pynq-z2/tcl_scripts/axi_stream_design.tcl

+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {Auto} Clk_slave {Auto} Clk_xbar {Auto} Master {/axi_dma_0/M_AXI_S2MM} Slave {/processing_system7_0/S_AXI_HP2} ddr_seg {Auto} intc_ip {New AXI Interconnect} master_apm {0}}  [get_bd_intf_pins processing_system7_0/S_AXI_HP2]
+apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config { Clk {/processing_system7_0/FCLK_CLK0 (50 MHz)} Freq {100} Ref_Clk0 {} Ref_Clk1 {} Ref_Clk2 {}}  [get_bd_pins myproject_axi_0/ap_clk]
+endgroup
+


I needed to add group_bd_cells hier_0 [get_bd_cells axi_dma_0] [get_bd_cells ${project_name}_axi_0] here because axi_stream_driver.py expect an IP hierarchy hier_0.

steltze and others added 30 commits April 19, 2024 10:31

Initial commit

312832f

Set change the backend

d2b5a15

Change the accelerator config script

02659dd

Set the vitis accelerator template

56296b6

Set vitis accelerator writer

7dd0173

Fix writes init

6f181b8

Include separable convolution resource implementation

bd2e52e

Separate depthwise resource strategy to 3 cases

b795240

Complete vitis accelerator wrapper for io_stream case

eeb04d4

Fix call to wrong backend writer

7e47c85

Fix vitis accelerator writer

5a2a38f

Fix include in axi wrapper header file writer

99f9429

Change python-cpp bridge writer

b9609dc

Fix tlast handling in axis wrapper writer

4f69c16

Extend convert_data to handle stream type, use that for the bridge

014a7b2

Add zcu102 to the supported boards json

723073e

Fix some c synthesis warnings

290896b

Group more tests per YAML to reduce the number of envs created

c9dfcf2

Support negative_slope in quantized_relu

d3b8e20

[pre-commit.ci] auto fixes from pre-commit hooks

b32984f

Fix activation check in profiling

98273a0

[pre-commit.ci] pre-commit autoupdate

2a71a83

updates: - [github.com/psf/black: 24.3.0 → 24.4.0](psf/black@24.3.0...24.4.0)

fix unwanted tested file change in fastmachinelearning#956

6ac964c

Fix SR backend synth missing variables

ec95e01

Test for SR backend config

5de1bf5

Upsampling support for PyTorch models

a6fec36

Split Catapult types into separate file

1b72b19

Split Quartus types into separate file

28521d0

Split Vivado types into separate file

a44707d

nghielme reviewed Nov 21, 2024

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hls4ml/templates/vitis/nnet_utils/nnet_sepconv1d_stream.h Outdated Show resolved Hide resolved

nghielme reviewed Nov 21, 2024

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hls4ml/templates/vitis/nnet_utils/nnet_sepconv2d_stream.h Outdated Show resolved Hide resolved

steltze added 6 commits November 27, 2024 09:58

Clean backends init

f467829

Fix backend import sequence

4c74550

Start cleaning up code

542b950

Start integrating FIFO depth optimizer

c78aec2

Fix FIFO depth optimizer

62b5c27

Run precommit

d5f2192

steltze marked this pull request as ready for review February 20, 2025 14:25

steltze added 2 commits February 20, 2025 16:26

Merge branch 'main' into vitis_accelerator_ip_flow

34b0929

Update build_prj.tcl

14b413e

nghielme reviewed Feb 22, 2025

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hls4ml/backends/vitis_accelerator_ip_flow/vitis_accelerator_ip_flow_backend.py Outdated Show resolved Hide resolved

nghielme reviewed Feb 22, 2025

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test/pytest/test_optimization/test_fifo_depth.py Outdated Show resolved Hide resolved

nghielme reviewed Mar 3, 2025

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hls4ml/templates/vitis_accelerator_ip_flow/build_lib.sh Outdated Show resolved Hide resolved

nghielme reviewed Mar 3, 2025

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steltze and others added 6 commits March 6, 2025 17:00

Merge branch 'main' into vitis_accelerator_ip_flow

800423f

Address pr comments and merge main

9f1c8b3

Include tests without fifo optimization and checks for bitstream gene…

4763692

…ration

Run precommit and remove unused override testbench

e66ad40

Fix qonnx test

f51be88

Fix keras fifo optimization test

85c233c

nghielme added the please test Trigger testing by creating local PR branch label Mar 7, 2025

steltze and others added 5 commits March 7, 2025 14:20

Fix test documentation

b91b641

Fix vivado project path in the build tcl for zcu102

5bc54d3

Skip all tests

0a0d7d1

Merge branch 'main' into vitis_accelerator_ip_flow

da4f8b5

Link backend fifo optimization options

e55c52e

DivineMK reviewed Mar 28, 2025

View reviewed changes

jmitrevs mentioned this pull request May 1, 2025

Vivado 2020.2 fastmachinelearning/hls4ml-tutorial#101

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Vitis Accelerator IP Flow #1134

Vitis Accelerator IP Flow #1134

steltze commented Nov 20, 2024 •

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nghielme Feb 22, 2025 •

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steltze Mar 3, 2025

jmitrevs Mar 3, 2025 •

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nghielme Mar 3, 2025

DivineMK Mar 28, 2025

Vitis Accelerator IP Flow #1134

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Vitis Accelerator IP Flow #1134

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steltze commented Nov 20, 2024 • edited Loading

Type of change

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Checklist

nghielme Feb 22, 2025 • edited Loading

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steltze commented Nov 20, 2024 •

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