Skip to content

Commit dce0b37

Browse files
committed
Verilog: __FILE__ and __LINE__
This adds 1800 2017 22.13 `__FILE__ and `__LINE__ to the Verilog preprocessor.
1 parent f6c38d9 commit dce0b37

File tree

5 files changed

+83
-45
lines changed

5 files changed

+83
-45
lines changed
Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
CORE
2+
file1.v
3+
--preprocess
4+
^ "file1\.v", 4\);$
5+
^EXIT=0$
6+
^SIGNAL=0$
7+
--
8+
^PREPROCESSING FAILED$
Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
module main;
2+
3+
initial $display("Internal error: null handle at %s, line %d.",
4+
`__FILE__, `__LINE__);
5+
6+
endmodule

src/verilog/expr2verilog.cpp

Lines changed: 54 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,59 @@ Author: Daniel Kroening, [email protected]
2727
#include <iomanip>
2828
#include <sstream>
2929

30+
std::string verilog_string_literal(const std::string &src)
31+
{
32+
std::string dest;
33+
34+
dest = '"';
35+
36+
for(auto &ch : src)
37+
{
38+
// Follows Table Table 5-1 in 1800-2017.
39+
switch(ch)
40+
{
41+
case '\n':
42+
dest += "\\n";
43+
break;
44+
case '\t':
45+
dest += "\\t";
46+
break;
47+
case '\\':
48+
dest += "\\\\";
49+
break;
50+
case '"':
51+
dest += "\\\"";
52+
break;
53+
case '\v':
54+
dest += "\\v";
55+
break;
56+
case '\f':
57+
dest += "\\f";
58+
break;
59+
case '\a':
60+
dest += "\\a";
61+
break;
62+
default:
63+
if(
64+
(unsigned(ch) >= ' ' && unsigned(ch) <= 126) ||
65+
(unsigned(ch) >= 128 && unsigned(ch) <= 254))
66+
{
67+
dest += ch;
68+
}
69+
else
70+
{
71+
std::ostringstream oss;
72+
oss << "\\x" << std::setw(2) << std::setfill('0') << std::hex << ch;
73+
dest += oss.str();
74+
}
75+
}
76+
}
77+
78+
dest += '"';
79+
80+
return dest;
81+
}
82+
3083
/*******************************************************************\
3184
3285
Function: expr2verilogt::convert_if
@@ -1214,51 +1267,7 @@ expr2verilogt::resultt expr2verilogt::convert_constant(
12141267
}
12151268
else if(type.id() == ID_string)
12161269
{
1217-
dest = '"';
1218-
1219-
for(auto &ch : id2string(src.get_value()))
1220-
{
1221-
// Follows Table Table 5-1 in 1800-2017.
1222-
switch(ch)
1223-
{
1224-
case '\n':
1225-
dest += "\\n";
1226-
break;
1227-
case '\t':
1228-
dest += "\\t";
1229-
break;
1230-
case '\\':
1231-
dest += "\\\\";
1232-
break;
1233-
case '"':
1234-
dest += "\\\"";
1235-
break;
1236-
case '\v':
1237-
dest += "\\v";
1238-
break;
1239-
case '\f':
1240-
dest += "\\f";
1241-
break;
1242-
case '\a':
1243-
dest += "\\a";
1244-
break;
1245-
default:
1246-
if(
1247-
(unsigned(ch) >= ' ' && unsigned(ch) <= 126) ||
1248-
(unsigned(ch) >= 128 && unsigned(ch) <= 254))
1249-
{
1250-
dest += ch;
1251-
}
1252-
else
1253-
{
1254-
std::ostringstream oss;
1255-
oss << "\\x" << std::setw(2) << std::setfill('0') << std::hex << ch;
1256-
dest += oss.str();
1257-
}
1258-
}
1259-
}
1260-
1261-
dest += '"';
1270+
dest = verilog_string_literal(id2string(src.get_value()));
12621271
}
12631272
else if(type.id() == ID_verilog_chandle || type.id() == ID_verilog_event)
12641273
{

src/verilog/expr2verilog.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,3 +10,5 @@ Author: Daniel Kroening, [email protected]
1010

1111
std::string expr2verilog(const exprt &, const namespacet &);
1212
std::string type2verilog(const typet &, const namespacet &);
13+
14+
std::string verilog_string_literal(const std::string &);

src/verilog/verilog_preprocessor.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ Author: Daniel Kroening, [email protected]
1111
#include <util/config.h>
1212
#include <util/unicode.h>
1313

14+
#include "expr2verilog.h"
1415
#include "verilog_preprocessor_error.h"
1516

1617
#include <filesystem>
@@ -672,6 +673,18 @@ void verilog_preprocessort::directive()
672673
break;
673674
}
674675
}
676+
else if(text == "__FILE__")
677+
{
678+
// 1800 2017 22.13
679+
// String literal
680+
out << verilog_string_literal(context().filename_as_string());
681+
}
682+
else if(text == "__LINE__")
683+
{
684+
// 1800 2017 22.13
685+
// decimal number
686+
out << tokenizer().line_no();
687+
}
675688
else
676689
{
677690
// check defines

0 commit comments

Comments
 (0)