Verilog: KNOWNBUG test for continuous assignment to part select of net

This reproduces issue #638.

Author: kroening

regression/verilog/synthesis/continuous_assignment_to_net_part_select1.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+continuous_assignment_to_net_part_select1.sv
+--bound 0
+^\[main\.p0\] always main\.some_wire\[1:0\] == 1: PROVED up to bound 0$
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This reproduces https://github.com/diffblue/hw-cbmc/issues/638

regression/verilog/synthesis/continuous_assignment_to_net_part_select1.sv

@@ -0,0 +1,8 @@
+module main;
+
+  wire [31:0] some_wire;
+  assign some_wire[1:0] = 'b01;
+
+  p0: assert final (some_wire[1:0] == 1);
+
+endmodule