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2 | 2 | verilog2.sv
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3 | 3 | --smv-word-level
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4 | 4 | ^MODULE main$
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5 |
| -^INIT main\.sw1 = extend\(signed\(main\.ui\), 24\)$ |
6 |
| -^INIT main\.sw2 = extend\(main\.si, 24\)$ |
7 |
| -^INIT main\.uw1 = extend\(main\.ui, 24\)$ |
8 |
| -^INIT main\.uw2 = unsigned\(extend\(main\.si, 24\)\)$ |
9 |
| -^INIT main\.sn1 = signed\(resize\(main\.ui, 4\)\)$ |
10 |
| -^INIT main\.sn2 = signed\(resize\(unsigned\(main.si\), 4\)\)$ |
11 |
| -^INIT main\.un1 = resize\(main\.ui, 4\)$ |
12 |
| -^INIT main\.un2 = resize\(unsigned\(main\.si\), 4\)$ |
13 |
| -^INIT main\.sb1 = signed\(main\.ui\)$ |
14 |
| -^INIT main\.sb2 = main\.si$ |
15 |
| -^INIT main\.ub1 = main\.ui$ |
16 |
| -^INIT main\.ub2 = unsigned\(main\.si\)$ |
| 5 | +^INVAR main\.sw1 = extend\(signed\(main\.ui\), 24\)$ |
| 6 | +^INVAR main\.sw2 = extend\(main\.si, 24\)$ |
| 7 | +^INVAR main\.uw1 = extend\(main\.ui, 24\)$ |
| 8 | +^INVAR main\.uw2 = unsigned\(extend\(main\.si, 24\)\)$ |
| 9 | +^INVAR main\.sn1 = signed\(resize\(main\.ui, 4\)\)$ |
| 10 | +^INVAR main\.sn2 = signed\(resize\(unsigned\(main.si\), 4\)\)$ |
| 11 | +^INVAR main\.un1 = resize\(main\.ui, 4\)$ |
| 12 | +^INVAR main\.un2 = resize\(unsigned\(main\.si\), 4\)$ |
| 13 | +^INVAR main\.sb1 = signed\(main\.ui\)$ |
| 14 | +^INVAR main\.sb2 = main\.si$ |
| 15 | +^INVAR main\.ub1 = main\.ui$ |
| 16 | +^INVAR main\.ub2 = unsigned\(main\.si\)$ |
17 | 17 | ^EXIT=0$
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18 | 18 | ^SIGNAL=0$
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19 | 19 | --
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