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Merge pull request #326 from diffblue/verilog_ift
Verilog: verilog_ift interface
2 parents b0fa961 + 7706692 commit b1ffbf0

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3 files changed

+45
-38
lines changed

3 files changed

+45
-38
lines changed

src/verilog/verilog_expr.h

Lines changed: 33 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -784,51 +784,73 @@ inline verilog_caset &to_verilog_case(exprt &expr)
784784
class verilog_ift:public verilog_statementt
785785
{
786786
public:
787-
verilog_ift():verilog_statementt(ID_if)
787+
verilog_ift(exprt __cond, verilog_statementt __then_case)
788+
: verilog_statementt(ID_if)
788789
{
789-
operands().resize(3);
790+
add_to_operands(std::move(__cond), std::move(__then_case));
790791
}
791792

792-
exprt &condition()
793+
verilog_ift(
794+
exprt __cond,
795+
verilog_statementt __then_case,
796+
verilog_statementt __else_case)
797+
: verilog_statementt(ID_if)
798+
{
799+
add_to_operands(
800+
std::move(__cond), std::move(__then_case), std::move(__else_case));
801+
}
802+
803+
exprt &cond()
793804
{
794805
return op0();
795806
}
796807

797-
const exprt &condition() const
808+
const exprt &cond() const
798809
{
799810
return op0();
800811
}
801-
802-
verilog_statementt &true_case()
812+
813+
verilog_statementt &then_case()
803814
{
804815
return static_cast<verilog_statementt &>(op1());
805816
}
806817

807-
const verilog_statementt &true_case() const
818+
const verilog_statementt &then_case() const
808819
{
809820
return static_cast<const verilog_statementt &>(op1());
810821
}
811822

812-
verilog_statementt &false_case()
823+
bool has_else_case() const
824+
{
825+
return operands().size() == 3;
826+
}
827+
828+
verilog_statementt &else_case()
813829
{
814830
return static_cast<verilog_statementt &>(op2());
815831
}
816832

817-
const verilog_statementt &false_case() const
833+
const verilog_statementt &else_case() const
818834
{
819835
return static_cast<const verilog_statementt &>(op2());
820836
}
821837
};
822838

823839
inline const verilog_ift &to_verilog_if(const exprt &expr)
824840
{
825-
assert(expr.id()==ID_if && expr.operands().size()>=2);
841+
PRECONDITION(expr.id() == ID_if);
842+
DATA_INVARIANT(
843+
expr.operands().size() == 2 || expr.operands().size() == 3,
844+
"if has two or three operands");
826845
return static_cast<const verilog_ift &>(expr);
827846
}
828847

829848
inline verilog_ift &to_verilog_if(exprt &expr)
830849
{
831-
assert(expr.id()==ID_if && expr.operands().size()>=2);
850+
PRECONDITION(expr.id() == ID_if);
851+
DATA_INVARIANT(
852+
expr.operands().size() == 2 || expr.operands().size() == 3,
853+
"if has two or three operands");
832854
return static_cast<verilog_ift &>(expr);
833855
}
834856

src/verilog/verilog_synthesis.cpp

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2067,19 +2067,11 @@ Function: verilog_synthesist::synth_if
20672067
void verilog_synthesist::synth_if(
20682068
const verilog_ift &statement)
20692069
{
2070-
if(statement.operands().size()!=2 &&
2071-
statement.operands().size()!=3)
2072-
{
2073-
error().source_location=statement.source_location();
2074-
error() << "if statement expected to have two or three operands" << eom;
2075-
throw 0;
2076-
}
2077-
2078-
auto if_operand = synth_expr(statement.condition(), symbol_statet::CURRENT);
2070+
auto if_operand = synth_expr(statement.cond(), symbol_statet::CURRENT);
20792071

20802072
if(if_operand.is_true())
20812073
{
2082-
synth_statement(statement.true_case());
2074+
synth_statement(statement.then_case());
20832075
return;
20842076
}
20852077

@@ -2091,17 +2083,17 @@ void verilog_synthesist::synth_if(
20912083
true_map.clear_changed();
20922084
false_map.clear_changed();
20932085

2094-
// true case
2086+
// 'then' case
20952087
{
20962088
value_map=&true_map;
2097-
synth_statement(statement.true_case());
2089+
synth_statement(statement.then_case());
20982090
}
2099-
2100-
// false case
2101-
if(statement.operands().size()==3)
2091+
2092+
// 'else' case
2093+
if(statement.has_else_case())
21022094
{
21032095
value_map=&false_map;
2104-
synth_statement(statement.false_case());
2096+
synth_statement(statement.else_case());
21052097
}
21062098

21072099
// restore and merge

src/verilog/verilog_typecheck.cpp

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1245,22 +1245,15 @@ Function: verilog_typecheckt::convert_if
12451245

12461246
void verilog_typecheckt::convert_if(verilog_ift &statement)
12471247
{
1248-
if(statement.operands().size()!=2 &&
1249-
statement.operands().size()!=3)
1250-
{
1251-
throw errort().with_location(statement.source_location())
1252-
<< "if statement expected to have two or three operands";
1253-
}
1254-
1255-
exprt &condition=statement.condition();
1248+
exprt &condition = statement.cond();
12561249

12571250
convert_expr(condition);
12581251
make_boolean(condition);
12591252

1260-
convert_statement(statement.true_case());
1253+
convert_statement(statement.then_case());
12611254

1262-
if(statement.operands().size()==3)
1263-
convert_statement(statement.false_case());
1255+
if(statement.has_else_case())
1256+
convert_statement(statement.else_case());
12641257
}
12651258

12661259
/*******************************************************************\

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