Merge pull request #316 from diffblue/typed-parameter-ports

typed parameter ports

Author: kroening

regression/verilog/modules/parameter_ports2.desc

@@ -0,0 +1,7 @@
+KNOWNBUG
+parameter_ports2.v
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+The type of the parameter needs to be processed.

regression/verilog/modules/parameter_ports2.v

@@ -0,0 +1,11 @@
+module sub #(parameter an_eight_bit_parameter_port = 1)();
+
+  always assert p1: $bits(an_eight_bit_parameter_port) == 8;
+
+endmodule
+
+module main;
+
+  sub #(123) submodule();
+
+endmodule // main

src/verilog/parser.y

@@ -1490,8 +1490,8 @@ list_of_variable_identifiers:
 // This rule is more permissive that the grammar in the standard
 // to cover list_of_param_assignments.
 parameter_port_declaration:
-          TOK_PARAMETER param_assignment
-		{ $$ = $2; }
+          TOK_PARAMETER data_type_or_implicit param_assignment
+		{ $$ = $3; }
 	| data_type param_assignment
 		{ $$ = $2; }
 	| param_assignment