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tautschnigtautschnig
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Merge pull request #218 from diffblue/verilog-missing
Verilog: add missing operators and keywords
2 parents 1f4eb8c + 453eefd commit ab25eb4

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3 files changed

+28
-3
lines changed

3 files changed

+28
-3
lines changed

‎src/verilog/parser.y

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -270,6 +270,7 @@ int yyverilogerror(const char *error)
270270
%token TOK_GREATERGREATERGREATER ">>>"
271271
%token TOK_LESSLESS "<<"
272272
%token TOK_LESSLESSLESS "<<<"
273+
%token TOK_LESSMINUSGREATER "<->"
273274

274275
/* Unary or binary */
275276
%token TOK_PLUS "+"
@@ -436,6 +437,7 @@ int yyverilogerror(const char *error)
436437
%token TOK_BYTE "byte"
437438
%token TOK_CHANDLE "chandle"
438439
%token TOK_CHECKER "checker"
440+
%token TOK_CELL "cell"
439441
%token TOK_CLASS "class"
440442
%token TOK_CLOCKING "clocking"
441443
%token TOK_CONFIG "config"
@@ -447,8 +449,10 @@ int yyverilogerror(const char *error)
447449
%token TOK_COVERGROUP "covergroup"
448450
%token TOK_COVERPOINT "coverpoint"
449451
%token TOK_CROSS "cross"
452+
%token TOK_DESIGN "design"
450453
%token TOK_DIST "dist"
451454
%token TOK_DO "do"
455+
%token TOK_ENDCHECKER "endchecker"
452456
%token TOK_ENDCLASS "endclass"
453457
%token TOK_ENDCLOCKING "endclocking"
454458
%token TOK_ENDCONFIG "endconfig"
@@ -470,6 +474,8 @@ int yyverilogerror(const char *error)
470474
%token TOK_IFF "iff"
471475
%token TOK_IGNORE_BINS "ignore_bins"
472476
%token TOK_ILLEGAL_BINS "illegal_bins"
477+
%token TOK_IMPLEMENTS "implements"
478+
%token TOK_IMPLIES "implies"
473479
%token TOK_IMPORT "import"
474480
%token TOK_INSIDE "inside"
475481
%token TOK_INT "int"
@@ -506,6 +512,7 @@ int yyverilogerror(const char *error)
506512
%token TOK_SEQUENCE "sequence"
507513
%token TOK_SHORTINT "shortint"
508514
%token TOK_SHORTREAL "shortreal"
515+
%token TOK_SHOWCANCELLED "showcancelled"
509516
%token TOK_SOLVE "solve"
510517
%token TOK_STATIC "static"
511518
%token TOK_STRING "string"
@@ -520,8 +527,10 @@ int yyverilogerror(const char *error)
520527
%token TOK_TYPEDEF "typedef"
521528
%token TOK_UNION "union"
522529
%token TOK_UNIQUE "unique"
530+
%token TOK_UNIQUE0 "unique0"
523531
%token TOK_UNTIL "until"
524532
%token TOK_UNTIL_WITH "until_with"
533+
%token TOK_UNTYPED "untyped"
525534
%token TOK_VAR "var"
526535
%token TOK_VIRTUAL "virtual"
527536
%token TOK_VOID "void"
@@ -1560,8 +1569,8 @@ property_expr:
15601569
| property_expr "until_with" property_expr { init($$, "sva_until_with"); mto($$, $1); mto($$, $3); }
15611570
| property_expr "s_until" property_expr { init($$, "sva_s_until"); mto($$, $1); mto($$, $3); }
15621571
| property_expr "s_until_with" property_expr { init($$, "sva_s_until_with"); mto($$, $1); mto($$, $3); }
1563-
// | property_expr "implies" property_expr { init($$, ID_implies); mto($$, $1); mto($$, $3); }
1564-
// | property_expr "iff" property_expr { init($$, ID_iff); mto($$, $1); mto($$, $3); }
1572+
| property_expr "implies" property_expr { init($$, ID_implies); mto($$, $1); mto($$, $3); }
1573+
| property_expr "iff" property_expr { init($$, ID_iff); mto($$, $1); mto($$, $3); }
15651574
| "accept_on" '(' expression_or_dist ')' { init($$, "sva_accept_on"); mto($$, $3); }
15661575
| "reject_on" '(' expression_or_dist ')' { init($$, "sva_reject_on"); mto($$, $3); }
15671576
| "sync_accept_on" '(' expression_or_dist ')' { init($$, "sva_sync_accept_on"); mto($$, $3); }
@@ -2640,6 +2649,10 @@ expression:
26402649
| unary_operator attribute_instance_brace primary
26412650
{ $$=$1; mto($$, $3); }
26422651
| inc_or_dec_expression
2652+
| expression "->" expression
2653+
{ init($$, ID_implies); mto($$, $1); mto($$, $3); }
2654+
| expression "<->" expression
2655+
{ init($$, ID_iff); mto($$, $1); mto($$, $3); }
26432656
| expression TOK_PLUS expression
26442657
{ init($$, ID_plus); mto($$, $1); mto($$, $3); }
26452658
| expression TOK_MINUS expression

‎src/verilog/scanner.l

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -204,6 +204,7 @@ void verilog_scanner_init()
204204
">>>" { return TOK_GREATERGREATERGREATER; }
205205
"<<" { return TOK_LESSLESS; }
206206
"<<<" { return TOK_LESSLESSLESS; }
207+
"<->" { return TOK_LESSMINUSGREATER; }
207208

208209
/* Trinary operators */
209210

@@ -442,10 +443,12 @@ binsof { SYSTEM_VERILOG_KEYWORD(TOK_BINSOF); }
442443
bit { SYSTEM_VERILOG_KEYWORD(TOK_BIT); }
443444
break { SYSTEM_VERILOG_KEYWORD(TOK_BREAK); }
444445
byte { SYSTEM_VERILOG_KEYWORD(TOK_BYTE); }
446+
cell { SYSTEM_VERILOG_KEYWORD(TOK_CELL); }
445447
chandle { SYSTEM_VERILOG_KEYWORD(TOK_CHANDLE); }
446448
checker { SYSTEM_VERILOG_KEYWORD(TOK_CHECKER); }
447449
class { SYSTEM_VERILOG_KEYWORD(TOK_CLASS); }
448450
clocking { SYSTEM_VERILOG_KEYWORD(TOK_CLOCKING); }
451+
config { SYSTEM_VERILOG_KEYWORD(TOK_CONFIG); }
449452
const { SYSTEM_VERILOG_KEYWORD(TOK_CONST); }
450453
constraint { SYSTEM_VERILOG_KEYWORD(TOK_CONSTRAINT); }
451454
context { SYSTEM_VERILOG_KEYWORD(TOK_CONTEXT); }
@@ -454,8 +457,10 @@ cover { SYSTEM_VERILOG_KEYWORD(TOK_COVER); }
454457
covergroup { SYSTEM_VERILOG_KEYWORD(TOK_COVERGROUP); }
455458
coverpoint { SYSTEM_VERILOG_KEYWORD(TOK_COVERPOINT); }
456459
cross { SYSTEM_VERILOG_KEYWORD(TOK_CROSS); }
460+
design { SYSTEM_VERILOG_KEYWORD(TOK_DESIGN); }
457461
dist { SYSTEM_VERILOG_KEYWORD(TOK_DIST); }
458462
do { SYSTEM_VERILOG_KEYWORD(TOK_DO); }
463+
endchecker { SYSTEM_VERILOG_KEYWORD(TOK_ENDCHECKER); }
459464
endclass { SYSTEM_VERILOG_KEYWORD(TOK_ENDCLASS); }
460465
endclocking { SYSTEM_VERILOG_KEYWORD(TOK_ENDCLOCKING); }
461466
endgroup { SYSTEM_VERILOG_KEYWORD(TOK_ENDGROUP); }
@@ -476,6 +481,8 @@ foreach { SYSTEM_VERILOG_KEYWORD(TOK_FOREACH); }
476481
iff { SYSTEM_VERILOG_KEYWORD(TOK_IFF); }
477482
ignore_bins { SYSTEM_VERILOG_KEYWORD(TOK_IGNORE_BINS); }
478483
illegal_bins { SYSTEM_VERILOG_KEYWORD(TOK_ILLEGAL_BINS); }
484+
implements { SYSTEM_VERILOG_KEYWORD(TOK_IMPLEMENTS); }
485+
implies { SYSTEM_VERILOG_KEYWORD(TOK_IMPLIES); }
479486
import { SYSTEM_VERILOG_KEYWORD(TOK_IMPORT); }
480487
inside { SYSTEM_VERILOG_KEYWORD(TOK_INSIDE); }
481488
int { SYSTEM_VERILOG_KEYWORD(TOK_INT); }
@@ -512,6 +519,7 @@ s_until_with { SYSTEM_VERILOG_KEYWORD(TOK_S_UNTIL_WITH); }
512519
sequence { SYSTEM_VERILOG_KEYWORD(TOK_SEQUENCE); }
513520
shortint { SYSTEM_VERILOG_KEYWORD(TOK_SHORTINT); }
514521
shortreal { SYSTEM_VERILOG_KEYWORD(TOK_SHORTREAL); }
522+
showcancelled { SYSTEM_VERILOG_KEYWORD(TOK_SHOWCANCELLED); }
515523
solve { SYSTEM_VERILOG_KEYWORD(TOK_SOLVE); }
516524
static { SYSTEM_VERILOG_KEYWORD(TOK_STATIC); }
517525
string { SYSTEM_VERILOG_KEYWORD(TOK_STRING); }
@@ -526,8 +534,10 @@ type { SYSTEM_VERILOG_KEYWORD(TOK_TYPE); }
526534
typedef { VIS_VERILOG_KEYWORD(TOK_TYPEDEF); }
527535
union { SYSTEM_VERILOG_KEYWORD(TOK_UNION); }
528536
unique { SYSTEM_VERILOG_KEYWORD(TOK_UNIQUE); }
537+
unique0 { SYSTEM_VERILOG_KEYWORD(TOK_UNIQUE0); }
529538
until { SYSTEM_VERILOG_KEYWORD(TOK_UNTIL); }
530539
until_with { SYSTEM_VERILOG_KEYWORD(TOK_UNTIL_WITH); }
540+
untyped { SYSTEM_VERILOG_KEYWORD(TOK_UNTYPED); }
531541
var { SYSTEM_VERILOG_KEYWORD(TOK_VAR); }
532542
virtual { SYSTEM_VERILOG_KEYWORD(TOK_VIRTUAL); }
533543
void { SYSTEM_VERILOG_KEYWORD(TOK_VOID); }

‎src/verilog/verilog_typecheck_expr.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1906,7 +1906,9 @@ void verilog_typecheck_exprt::convert_binary_expr(binary_exprt &expr)
19061906
convert_extractbit_expr(to_extractbit_expr(expr));
19071907
else if(expr.id()==ID_replication)
19081908
convert_replication_expr(to_replication_expr(expr));
1909-
else if(expr.id()==ID_and || expr.id()==ID_or)
1909+
else if(
1910+
expr.id() == ID_and || expr.id() == ID_or || expr.id() == ID_iff ||
1911+
expr.id() == ID_implies)
19101912
{
19111913
Forall_operands(it, expr)
19121914
{

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